IS61LV256-15J ISSI, Integrated Silicon Solution Inc, IS61LV256-15J Datasheet

IS61LV256-15J

Manufacturer Part Number

IS61LV256-15J

Description

SRAM 256K 32Kx8 15ns 3.3v

Manufacturer

ISSI, Integrated Silicon Solution Inc

Type

Asynchronousr

Datasheet

1.IS61LV256-15J.pdf (8 pages)

Specifications of IS61LV256-15J

Memory Size

256 Kbit

Access Time

15 ns

Package / Case

SOJ-28

Supply Voltage (max)

3.63 V

Supply Voltage (min)

2.97 V

Maximum Operating Current

90 mA

Organization

32 K x 8

Interface

TTL

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Number Of Ports

Operating Supply Voltage

3.3 V

Lead Free Status / Rohs Status

Available stocks

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Manufacturer

Quantity

Price

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ISSI

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ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which

IS61LV256

FEATURES

• High-speed access time: 12, 15, 20, 25 ns

• Automatic power-down when chip is deselected

• CMOS low power operation

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh

• Three-state outputs

Integrated Silicon Solution, Inc.

Rev. F 0296

SR81995LV61

IS61LV256

32K x 8 LOW VOLTAGE CMOS STATIC RAM

— 345 mW (max.) operating

— 7 mW (max.) CMOS standby

required

FUNCTIONAL BLOCK DIAGRAM

I/O0-I/O7

A0-A14

GND

VCC

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

DESCRIPTION

The

32,768-word by 8-bit static RAM. It is fabricated using

high-performance CMOS technology. This highly reliable pro-

cess coupled with innovative circuit design techniques, yields

access times as fast as 12 ns maximum.

When

mode at which the power dissipation is reduced to

50 W (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Enable (

both writing and reading of the memory.

The IS61LV256 is available in the JEDEC standard 28-pin,

300-mil DIP and SOJ, plus the 450-mil TSOP package.

ISSI

is HIGH (deselected), the device assumes a standby

IS61LV256 is a very high-speed, low power,

MEMORY ARRAY

COLUMN I/O

256 X 1024

). The active LOW Write Enable (

FEBRUARY 1996

ISSI

) controls

ISSI

2-1

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