DS2431 Maxim Integrated Products, DS2431 Datasheet

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... GENERAL DESCRIPTION The DS2431 is a 1024-bit, 1-Wire organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from state. ...

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... Standard speed Overdrive speed (Note 5, 19) (Note 20, 21) At 25° 85°C (worst case) At 85°C (worst case DS2431: 1024-Bit, 1-Wire EEPROM -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C See IPC/JEDEC J-STD-020A (T = -40°C to +85°C; see Note 1.) ...

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... Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to t Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS2431 present. Minimum limit RSTL maximum limit is t PDH(max) Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. ...

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... Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the register page ...

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... Commands (see Figure 7) 64-BIT LASERED ROM Each DS2431 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See Figure 3 for details ...

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... Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS2431 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into 4 memory pages (32 bytes each). These 4 pages are the primary data memory. ...

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... ADDRESS REGISTERS AND TRANSFER STATUS The DS2431 employs three address registers: TA1, TA2, and E/S (Figure 6). These registers are common to many other 1-Wire devices but operate slightly differently with the DS2431. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read ...

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... The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the DS2431. An example on how to use these functions to write to and read from the device is included at the end of this document. The communication between master and DS2431 takes place either at regular speed (default Overdrive Speed ( ...

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... Part Applies only if the memory area is not protected. If write-protected, then the DS2431 copies the data byte from the tar- get address into the SP EPROM mode, then the DS2431 loads the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the SP ...

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... E/S Byte DS2431 sets Scratchpad Byte Counter = T2:T0 Bus Master RX Data Byte from Scratchpad Y Master TX Reset ? N N Byte Counter = E2: Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS2431 N Master TX Reset ? DS2431: 1024-Bit, 1-Wire EEPROM To Figure Part From Figure Part ...

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... TX Reset ? To Figure Part 55h N Pad ? Y Applicable to all R/W memory locations. Y T15:T0 < 0090h ? N N Duration Master Y * 1-Wire idle high for power DS2431: 1024-Bit, 1-Wire EEPROM To Figure Part Copy- Protected ? DS2431 copies Scratch- PROG pad Data to Address DS2431 TX “0” Y Master TX Reset ? N DS2431 TX “1” ...

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... To Figure Part DS2431 sets Memory Address = (T15:T0) DS2431 Bus Master RX Increments Data Byte from Address Memory Address Counter Master TX Reset ? N Y Address < 8Fh ? N N Bus Master Master RX “1”s TX Reset ? DS2431: 1024-Bit, 1-Wire EEPROM Y Bus Master RX “1”s N Master TX Reset ? Y ...

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... The device's internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command. 1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2431 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing) ...

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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2431 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ...

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... The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS2431 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS2431 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command ...

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... Match ROM Search ROM Command ? Command ? DS2431 TX Bit 0 Master TX Bit 0 DS2431 TX Bit 0 Master TX Bit Bit 0 Bit 0 Match ? Match ? Y DS2431 TX Bit 1 Master TX Bit 1 DS2431 TX Bit 1 Master TX Bit Bit 1 Bit 1 Match ? Match ? Y DS2431 TX Bit 63 Master TX Bit 63 DS2431 TX Bit 63 Master TX Bit Bit 63 Bit 63 Match ? Match ? Y ...

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... Part Resume Command ? From Figure Part To Figure Part 3Ch N N Overdrive Skip ROM ? Master TX Reset ? N Y Master TX Reset ? DS2431: 1024-Bit, 1-Wire EEPROM 69h N Overdrive Match ROM ? Master TX Bit 0 N Bit Match ? Y Master TX Bit 1 N Bit Match ? Y Master TX Bit 63 N Bit Match ? ...

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... Figure 10 shows the initialization sequence required to begin any communication with the DS2431. A Reset Pulse followed by a Presence Pulse indicates the DS2431 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for compensate for the edge ...

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... For a write-zero time slot, the voltage on the data line must stay below the V W1LMAX threshold until the write-zero low time t data line should not exceed V ILMAX the DS2431 needs a recovery time t Figure 11. Read/Write Timing Diagram Write-One Time Slot t V PUP ...

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... RL line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS2431 does not hold the data line low at all, and the voltage starts rising as soon as t over. + δ (rise time) on one side and the internal timing generator of the DS2431 on the other side define ...

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... CRC GENERATION With the DS2431 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2431 to determine if the ROM data has been received error- free ...

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... COPY SCRATCHPAD (INVALID ADDRESS COPY PROTECTED) RST PD Select CPS READ MEMORY (SUCCESS) RST PD Select RM Programming DESCRIPTION TA <8 – T2:T0 bytes> CRC16\ TA-E/S <8 – T2:T0 bytes> TA-E/S Programming AA loop TA-E/S FF loop TA <data to EOM> FF loop DS2431: 1024-Bit, 1-Wire EEPROM FF loop CRC16\ FF loop ...

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... READ MEMORY (INVALID ADDRESS) RST PD Select RM MEMORY FUNCTION EXAMPLE Write to the first 8 bytes of memory page 1. Read the entire memory. With only a single DS2431 connected to the bus master, the communication looks like this: MASTER MODE ---- loop DATA (LSB FIRST) (Reset) (Presence) CCh ...

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... N.C. The leads of TO-92 packages (standard and lead- free) on tape-and-reel are formed to approximately 4 N.C. 100-mil (2.54mm) spacing. For details refer to drawing 56-G0006-003. 21-0137 DS2431: 1024-Bit, 1-Wire EEPROM PART TEMP RANGE PIN-PACKAGE -40°C to +85°C SFN -40°C to +85°C SFN, tape-and-reel TDFN*, 2.5k pcs, -40° ...