MAX2741ETI Maxim Integrated Products, MAX2741ETI Datasheet
MAX2741ETI
Specifications of MAX2741ETI
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MAX2741ETI Summary of contents
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... Integrated Synthesizer and VCO ♦ Integrated 2- or 3-Bit ADC ♦ 50dB IF AGC Range ♦ Small 28-Pin Thin QFN Package ♦ SPI™ Control Interface ♦ Clock Output for Baseband Processor SPI is a trademark of Motorola, Inc. PART MAX2741ETI Applications N.C. 2 RFIN ...
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Integrated L1-Band GPS Receiver ABSOLUTE MAXIMUM RATINGS V Pins to GND ...................................................-0.3V to +3. Pins to Each Other .........................................-0.3V to +0.3V CC FILT to GND................................................-0. CMOS Inputs to GND (SHDN, SCLK, CS, SDI).................................................+0. CMOS ...
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AC ELECTRICAL CHARACTERISTICS (continued) (Operating conditions (unless otherwise specified): V 1.2V ; registers set according to mode; using the Typical Application Circuit signal at 1575.42MHz. Typical values are mea- P-P sured 2.75V +25°C.) ...
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Integrated L1-Band GPS Receiver PIN NAME LNA Supply Connection. External RF bypass capacitor to ground required 20, 22, 23 N.C. Reserved. Make no connections to this pin. LNA Input. Connect to GPS antenna through a ...
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Detailed Description The MAX2741 GPS offers a high-performance super- heterodyne receiver solution for low-power mobile devices, with the benefit of using the system’s existing clock reference. This receiver is ideal for integration into mobile phone handsets using common reference fre- ...
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Integrated L1-Band GPS Receiver MAX2741 GND 22nF 100pF 36kΩ Figure 1. Recommended 3rd-Order PLL Filter The VCO offers a bank of tuning capacitors that can be latched in/out to adjust the center frequency. ...
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Table 2. Register Address and Data Bit Assigments (Write) REGISTER NAME D15 D14 D13 D12 D11 D10 SYNTH CONFIG 1 CONFIG 2 Table 3. Register Address and Data Bit Assigments (Read) REGISTER NAME D15 D14 D13 D12 D11 D10 STATUS ...
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Integrated L1-Band GPS Receiver Detailed Register Definitions Table 4. Detailed Register Definition for Write Address 0100: SYNTH DATA BIT DEFAULT D15 1 Reserved D14 1 LPF Autotune Initiate Initiate autotune Manual tuning. D13–D10 0100 LPF Tuning ...
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Table 7. Detailed Register Definition for Read Address 0111: STATUS DATA BIT DEFAULT D15–D10 XXXXXX Reserved Out-of-Lock (High Frequency PLL is out of lock, VCO free-running at its highest frequency Locked. Out-of-Lock (Low Frequency): ...
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Integrated L1-Band GPS Receiver N.C. 2 RFIN GND 7 All I/O connections are DC-coupled. Supply voltages as specified in the electrical specifications. I/O ...
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V CC 100pF 22pF 100pF 6.2nH GPS RF INPUT FROM GPS BPF 2.2pF V CC 100pF 22pF V CC 1nF 100pF V CC 100nF 100pF 22nF 36kΩ Table 9. Digital Test-Mode-Select Description REGISTER SETTING MODE CONFIG1: ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products D ...