FM1808-70-S Ramtron, FM1808-70-S Datasheet - Page 5
![F-RAM 256K (32Kx8) 70ns 5V](/photos/40/60/406083/soic-28-fram_sml.jpg)
FM1808-70-S
Manufacturer Part Number
FM1808-70-S
Description
F-RAM 256K (32Kx8) 70ns 5V
Manufacturer
Ramtron
Datasheet
1.FM1808-70-S.pdf
(12 pages)
Specifications of FM1808-70-S
Memory Size
256 KB
Organization
32 K x 8
Interface
Parallel
Access Time
70 ns
Operating Supply Voltage
0 V to + 5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
SOIC-28
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
No
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A second design consideration relates to the level of
V
forced to monitor V
backup. They typically block user access below a
certain V
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
nonvolatile memory in a power down situation with
no warning or indication.
F-RAM memories do not need this system overhead.
The memory will not block access at any V
The user, however, should prevent the processor from
accessing memory when V
common design practice of holding a processor in
reset during powerdown may be sufficient.
recommended that Chip Enable is pulled high and
allowed to track V
cycles. It is the user’s responsibility to ensure that
chip enable is high to prevent accesses below V
min. (4.5V). Figure 3 shows a pullup resistor on /CE
Rev. 3.5
Nov. 2010
DD
during operation. Battery-backed SRAMs are
DD
level in order to prevent loading the
DD
DD
during powerup and powerdown
in order to switch to battery
DD
is out-of-tolerance. The
DD
level.
It is
DD
which will keep the pin high during power cycles
assuming the MCU/MPU pin tri-states during the
reset condition. The pullup resistor value should be
chosen to ensure the /CE pin tracks V
enough value that the current drawn when /CE is low
is not an issue.
MCU/
Figure 3. Use of Pullup Resistor on /CE
MPU
V
R
DD
FM1808
CE
WE
OE
A(14:0)
DQ
DD
Page 5 of 12
yet a high
FM1808