MAX1238EEE Maxim Integrated Products, MAX1238EEE Datasheet - Page 12

• Manufacturer Part Number: MAX1238EEE
• Description: ADC (A/D Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1238EEE

• Number Of Adc Inputs: 12
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 12 bit
• Interface Type: I2C
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Lead Free Status / Rohs Status: No

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX1236–MAX1239 continu-
ously wait for a START condition followed by their slave
address. When the MAX1236–MAX1239 recognize their
slave address, they are ready to accept or send data.
Please refer to the table in the ordering information sec-
tion for the factory programmed slave address of the
selected device. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX1236–MAX1239
(R/W = 0 selects a write condition, R/W = 1 selects a
read condition). After receiving the address, the
MAX1236–MAX1239 (slave) issues an acknowledge by
pulling SDA low for one clock cycle.
Figure 7. MAX1236/MAX1237 Slave Address Byte
12
Figure 8. F/S-Mode to HS-Mode Transfer
______________________________________________________________________________________
SDA
SCL
S
SDA
SCL
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
0
S
MAX1236/MAX1237
0
0
1
1
0
2
HS-MODE MASTER CODE
Slave Address
1
0
3
SLAVE ADDRESS
F/S-MODE
0
1
4
1
X
5
At power-up, the MAX1236–MAX1239 bus timing is set
for fast-mode (F/S-mode), which allows conversion rates
up to 22.2ksps. The MAX1236–MAX1239 must operate
in high-speed mode (HS-mode) to achieve conversion
rates up to 94.4ksps. Figure 1 shows the bus timing for
the MAX1236–MAX1239’s 2-wire interface.
At power-up, the MAX1236–MAX1239 bus timing is set
for F/S-mode. The bus master selects HS-mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the MAX1236–
MAX1239 issue a not-acknowledge, allowing SDA to be
pulled high for one clock cycle (Figure 8). After the not-
acknowledge, the MAX1236–MAX1239 are in HS-mode.
The bus master must then send a repeated START fol-
lowed by a slave address to initiate HS-mode communi-
cation. If the master generates a STOP condition, the
MAX1236–MAX1239 return to F/S-mode.
0
X
6
0
X
7
R/W
A
8
A
9
Sr
HS-MODE
Bus Timing
HS-Mode