A25L020M-F AMIC, A25L020M-F Datasheet - Page 17
![58T1302](/photos/18/98/189855/ge8sop05-40_sml.jpg)
A25L020M-F
Manufacturer Part Number
A25L020M-F
Description
58T1302
Manufacturer
AMIC
Datasheet
1.A25L020-F.pdf
(44 pages)
Specifications of A25L020M-F
Memory Type
Flash
Memory Size
2Mbit
Memory Configuration
2M X 1
Interface Type
Serial, SPI
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Rohs Compliant
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A25L020M-F
Manufacturer:
AMIC
Quantity:
20 000
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum
frequency f
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
(December, 2010, Version 1.6)
C
, during the falling edge of Serial Clock (C).
DIO
DIO
DO
DO
S
S
C
C
Note: Address bits A23 to A18 are Don’t Care, for A25L020.
32 33 34 35 36 37 38 39
7
Address bits A23 to A17 are Don’t Care, for A25L010.
Address bits A23 to A16 are Don’t Care, for A25L512
0 1
6 5 4
High Impedance
Dummy Byte
2 3 4
Instruction
3
2
5 6 7
1
0
S
MSB
40 41 42 43 44 45 46 47
7 6 5 4 3 2 1
MSB
) Low.
23 22 21
8
9
24-Bit Address
Data Out 1
10
16
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)
instruction is terminated by driving Chip Select (
Chip Select (
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.
3 2 1 0
28 29 30 31
A25L020/A25L010/A25L512 Series
0
S
0
MSB
) can be driven High at any time during data
7 6 5 4 3 2 1 0
Data Out 2
AMIC Technology Corp.
MSB
7
S
) High.