GS842Z36AGB-150 GSI TECHNOLOGY, GS842Z36AGB-150 Datasheet - Page 11

• Manufacturer Part Number: GS842Z36AGB-150
• Description: 58M6829
• Manufacturer: GSI TECHNOLOGY

Specifications of GS842Z36AGB-150

• Memory Size: 4Mbit
• Memory Configuration: 128K X 36
• Clock Frequency: 150MHz
• Access Time: 10ns
• Supply Voltage Range: 2.3V To 2.7V, 3V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 119
• Rohs Compliant: Yes

Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as V
on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.04b 1/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
1st address
4th address
CK
ZZ
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
tKC
tKC
10
11
00
01
tKH
tKH
00
01
10
11
Sleep Mode Timing Diagram
tKL
tKL
tZZS
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Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
tZZH
2nd address
3rd address
4th address
1st address
A[1:0] A[1:0] A[1:0] A[1:0]
GS842Z18/36AB-180/166/150/100
00
01
10
11
DD
tZZR
or V
01
00
11
10
DDQ
on pipelined parts and V
10
00
01
11
SB
© 2001, GSI Technology
2. The duration of
11
10
01
00
BPR 1999.05.18
SS
8