PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 10

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

LOGIC DIAGRAM (CONTINUED)
10
GND 10
I 6
I 5
I 7
I 8
7
8
9
6
32
39
40
47
48
55
56
63
0
0
3 4
3 4
7 8
7 8
11 12 15 16 19 20 23 24 27 28 31
11 12 15 16 19 20
PALCE16V8 and PALCE16V8Z Families
23 24 27 28 31
0 X
1 1
0 X
1 0
0 X
1 1
0 X
1 1
1 0
1 1
1 0
1 0
SG1
SL1
SG1
SL1
SG1
SG1
SL1
SL1
3
2
1
0
SL0
SL0
SL0
SL0
CLK OE
3
2
1
0
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
V CC
V CC
V CC
V CC
SG1
SG1
SG1
SG0
0 X
0 X
1 0
1 1
1 1
1 0
0 0
0 1
1 1
1 0
0 X
1 0
1 1
0 X
0 X
1 1
1 0
0 0
0 1
1 1
1 0
1 1
1 0
0 0
0 1
0 X
1 1
0 X
1 1
1 0
0 0
0 X
1 0
1 0
1 1
1 1
1 0
1 0
0 1
1 1
SL0
SL0
SL0
SL0
0
3
2
1
(concluded)
15
14
13
12
11
16493E-6
I/O 3
I/O 2
OE/I
I/O 1
I/O 0
9