SPD6729QCE Intel, SPD6729QCE Datasheet - Page 71
SPD6729QCE
Manufacturer Part Number
SPD6729QCE
Description
PCI To PC Card (PCMCIA) Controller 208-Pin MQFP
Manufacturer
Intel
Datasheet
1.SPD6729QCE.pdf
(116 pages)
Specifications of SPD6729QCE
Package
208MQFP
Operating Temperature
0 to 70 °C
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10.2
Datasheet
IRQ[XX]
Register Name: FIFO Control
Index: 17h
FIFO Status /
Flush FIFO
Figure 12. Pulse Mode Interrupts
RW:1
Bit 7
HI-Z = high impedance
Bit 3: Pulse System IRQ
This bit selects Level or Pulse mode operation of the IRQ[XX] pins (see
Bit 4: Speaker Enable
This bit determines whether the card -SPKR pin will drive SPKR_OUT* (see
Bit 7: Inpack Enable
The -INPACK function is not applicable in PCI bus environments. This bit is provided for
backward-compatibility. Its setting has no effect on operations of the PD6729.
FIFO Control
HI-Z
Bit 6
0
1
0
1
0
1
Interrupts are passed to the IRQ[XX] pin as level-sensitive.
When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in
allows for interrupt sharing.
SPKR_OUT* is three-stated.
SPKR_OUT* is driven from the XOR of -SPKR from each enabled socket.
-INPACK pin (see
-INPACK pin used to control data bus drivers during I/O read from the socket.
Bit 5
Driven low
Table
Bit 4
2) ignored.
Scratchpad Bits
RW:0000000
Driven high
PCI-to-PC Card (PCMCIA) Controller — PD6729
Bit 3
Bit 2
Register Compatibility Type: ext.
Table 1 on page
Bit 1
Table
Register Per: socket
3).
Figure 12
HI-Z
15).
Bit 0
and
71
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