CY7C019V-25AC Cypress Semiconductor Corp, CY7C019V-25AC Datasheet
CY7C019V-25AC
Specifications of CY7C019V-25AC
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CY7C019V-25AC Summary of contents
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... BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06044 Rev. *C • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • ...
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Functional Description The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided ...
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... Typical Standby Current for I SB1 (Both ports TTL level) Typical Standby Current for I SB3 (Both ports CMOS level) Note: 5. This pin is NC for CY7C018V. Document #: 38-06044 Rev. *C 100-Pin TQFP (Top View CY7C019V (128K x 9) CY7C018V (64K CY7C008V/009V CY7C008V/009V CY7C018V/019V CY7C018V/019V -15 15 125 35 10 µA ...
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... Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State............................–0. Notes: 6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document #: 38-06044 Rev. *C Chip Enable (CE is LOW when CE Read/Write Enable Output Enable Address (A – ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage ( Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage Current OZ ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [11 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description t R/W HIGH after BUSY HIGH (Slave) WH [17] t BUSY HIGH to Data Valid BDD [16] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t ...
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Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access DATA OUT I CC CURRENT I SB [19, 21, 22, 23] Read Cycle No. ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [28 R/W NOTE 30 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 24. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009V/19V R/W L INT R t INS Right Side Clears INT : R ADDRESS R ...
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Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access ...
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If both ports attempt to access the semaphore within t of each other, the semaphore will SPS Table 1. Non-Contending Read/Write Inputs CE R/W OE ...
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... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C019V-15AC CY7C019V-15AXC 20 CY7C019V-20AC CY7C019V-20AXC CY7C019V-20AI CY7C019V-20AXI 25 CY7C019V-25AC CY7C019V-25AXC Document #: 38-06044 Rev. *C Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 ...
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... Document #: 38-06044 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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... SZV Change from Spec number: 38-00669 to 38-06044 OOR Change pin 85 from BUSYL to BUSYR (pg. 3) RBI Power up requirements added to Maximum Ratings Information YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC CY7C008V/009V CY7C018V/019V Page ...