IS63LV1024-15K INTEGRATED SILICON SOLUTION (ISSI), IS63LV1024-15K Datasheet - Page 5

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IS63LV1024-15K

Manufacturer Part Number
IS63LV1024-15K
Description
SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 15ns 32-Pin SOJ
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS63LV1024-15K

Package
32SOJ
Timing Type
Asynchronous
Density
1 Mb
Typical Operating Supply Voltage
3.3 V
Address Bus Width
17 Bit
Number Of I/o Lines
8 Bit
Number Of Ports
1
Number Of Words
128K

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IS63LV1024
IS63LV1024L
READ CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
AC TEST LOADS
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. O
07/02/2010
Symbol
t
t
t
t
t
t
t
t
t
t
t
loading specified in Figure 1.
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
RC
OHA
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
AA
ACE
(2)
(2)
OUTPUT
(2)
(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power Up Time
CE to Power Down Time
Z
OUT
= 50 Ω
See Figures 1 and 2
V
0V to 3.0V
T
= 1.5V
1.5V
Unit
3 ns
50 Ω
Min.
1-800-379-4774
8
2
0
0
3
0
0
-8 ns
(1)
Figure 2
(Over Operating Range)
Max.
8
8
4
4
4
8
OUTPUT
Min.
10
2
0
0
3
0
0
-10 ns
3.3V
Including
Max.
10
10
10
5
5
5
jig and
scope
5 pF
317 Ω
Min.
12
2
0
0
3
0
0
-12 ns
Max.
351 Ω
12
12
12
6
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5

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