CY28301PVC Cypress Semiconductor Corp, CY28301PVC Datasheet
CY28301PVC
Specifications of CY28301PVC
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CY28301PVC Summary of contents
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... SCLK Logic Control Logic (FS0:4) PLL 1 PD# PLL2 /2 Cypress Semiconductor Corporation Document #: 38-07011 Rev. *C Key Specifications ® Solano/810E/810 CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ................................................... 500 ps CPU, 3V66 Output Skew:............................................ 175 ps SDRAM, APIC, 48-MHz Output Skew: ........................250 ps PCI Output Skew:........................................................ 500 ps CPU to SDRAM Skew (@ 133 MHz) ......................... ± ...
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Pin Definitions Pin Name Pin No. REF/FS1 PCI0 11 PCI1 12 PCI2/SEL24_48MHz# 13 PCI3:7 15, 16, 17, 19, 20 3V66_0 48MHz/FS0 34 24_48MHz 35 PD# 22 CPU0:1 52, 51 SDRAM0:11, 48, 47, ...
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Serial Data Interface The CY28301 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word Write, byte/word Read, block Write, and ...
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Table 3. Word Read and Word Write Protocol Word Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8-bits ‘1xxxxxxx’ stands for byte or word operation bit[6:0] ...
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CY28301 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 – Bits Byte 0: Control Register 0 Bit Pin# Bit 7 ...
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Byte 2: Control Register 2 Bit Pin# Bit 7 20 Bit 6 19 Bit 5 17 Bit 4 16 Bit 3 15 Bit 2 13 Bit 1 12 Bit 0 11 Byte 3: Control Register 3 Bit Pin# Bit 7 ...
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Byte 6: Vendor ID and Revision ID Register (Read-only) Bit Name Bit 7 Revision_ID3 Bit 6 Revision_ID2 Bit 5 Revision_ID1 Bit 4 Revision_ID0 Bit 3 Vendor_ID3 Bit 2 Vendor_ID2 Bit 1 Vendor _ID1 Bit 0 Vendor _ID0 Byte 7: Control ...
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Byte 9: Reserved Register (continued) Bit Name Bit 1 Reserved Bit 0 Reserved Byte 10: Reserved Register Bit Name Bit 7 CPU_Skew2 Bit 6 CPU_Skew1 Bit 5 CPU_Skew0 Bit 4 SDRAM_Skew2 Bit 3 SDRAM_Skew1 Bit 2 SDRAM_Skew0 Bit 1 AGP_Skew1 ...
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Byte 13: Reserved Register Bit Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved Byte 14: Reserved Register Bit Name Bit 7 Reserved Bit ...
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Byte 17: Reserved Register (continued) Bit Pin# Bit 5 – Bit 4 – Bit 3 – Bit 2 – Bit 1 – Table 5. Frequency Selections through HW Strap Option and Serial Data Interface Data Bytes Input Conditions FS1 FS0 ...
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DC Operating Requirements (continued) Parameter Description V = 3.3V ±5% DDQ3 V 3.3V Output High Voltage oh3 V 3.3V Output Low Voltage ol3 V = 3.3V ±5% DDQ3 V PCI Bus Output High Voltage poh3 V PCI Bus Output Low ...
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AC Electrical Characteristics Parameter Description CPUCLK T Host/CPUCLK Period Period T Host/CPUCLK High Time HIGH T Host/CPUCLK Low Time LOW T Host/CPUCLK Rise Time RISE T Host/CPUCLK Fall Time FALL SDRAM T SDRAM CLK Period Period T SDRAM CLK High ...
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Group Skew and Jitter Limits Output Group Pin-Pin Skew Max. CPU 175 ps SDRAM 250 ps APIC 250 ps 48MHz 250 ps 3V66 175 ps PCI 500 ps REF N/A Clock Output Wave 2.0 1.25 2.5V Clocking 0.4 Interface 3.3V ...
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... Ordering Information Ordering Code CY28301PVC 56-pin SSOP (300 mils) CY28301PVCT 56-pin SSOP (300 mils) - Tape and Reel Package Drawing and Dimension Intel is a registered trademark of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07011 Rev. *C © ...
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Document History Page Document Title: CY28301 Frequency Generator for Intel Document Number: 38-07011 ECN Issue REV. NO. Date ** 106533 06/27/01 *A 109365 11/06/01 *B 118785 09/25/02 *C 122717 12/21/02 Document #: 38-07011 Rev. *C ® Integrated Chipset Orig. of ...