MAX3378EEUD Maxim Integrated Products, MAX3378EEUD Datasheet - Page 11

• Manufacturer Part Number: MAX3378EEUD
• Description: Voltage Level Translator 14-Pin TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3378EEUD

• Package: 14TSSOP
• Logic Function: Voltage Level Translator
• Output Type: 3-State
• Operating Supply Voltage: 1.8/3.3 V

Figure 1c. Open-Drain Driving I/O V
For proper operation ensure that +1.65V ≤ V
+5.5V, +1.2V ≤ V
During power-up sequencing, V
not damage the device. During power-supply sequenc-
ing, when V
rent may be sourced, yet the device will not latch up.
The speed-up circuitry limits the maximum data rate for
devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family to 16Mbps. The maximum data rate
also depends heavily on the load capacitance (see the
Typical Operating Characteristics), output impedance
of the driver, and the operational voltage range (see the
Timing Characteristics table).
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E feature a one-shot generator that
decreases the rise time of the output. When triggered,
MOSFETs PU1 and PU2 turn on for a short time to pull up
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
I/O V
I/O V
L_
CC_
t
PD-VCC-LH
CC
t
RVCC
V
L
is floating and V
______________________________________________________________________________________
L
I/O V
AND MAX3390E–MAX3393E
≤ +5.5V, and V
MAX3372E–MAX3379E
Low-Voltage Level Translators in UCSP
L_
V
L
GND
V
CC
CC
Speed-Up Circuitry
I/O V
L
Level Translation
is powering up, a cur-
L
CC_
≥ (V
t
PD-VCC-HL
L
DATA
≤ (V
t
FVCC
CC
V
CC
R
LOAD
CC
+ 0.3V) will
+ 0.3V).
C
LOAD
CC
≤
Figure 1d. Open-Drain Driving I/O V
I/O V
Figure 2b). This greatly reduces the rise time and propa-
gation delay for the low-to-high transition. The scope
photo of Rail-to-Rail Driving for 8Mbps Operation in the
Typical Operating Characteristics shows the speed-up
circuitry in operation.
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
the MAX3390E–MAX3393E have internal rise-time
accelerators allowing operation up to 16Mbps. The
rise-time accelerators are present on both sides of the
device and act to speed up the rise time of the input
and output of the device, regardless of the direction of
the data. The triggering mechanism for these accelera-
tors is both level and edge sensitive. To prevent false
triggering of the rise-time accelerators, signal fall times
of less than 20ns/V are recommended for both the
inputs and outputs of the device. Under less noisy con-
ditions, longer signal fall times may be acceptable.
C
LOAD
I/O V
I/O V
L_
L_
CC_
and I/O V
R
LOAD
t
PD-VL-LH
V
DATA
t
RVL
L
CC_
I/O V
AND MAX3390E–MAX3393E
MAX3373E–MAX3376E,
MAX3378E/MAX3379E
L_
to their respective supplies (see
Rise-Time Accelerators
V
L
GND
V
CC
L
I/O V
CC_
t
PD-VL-HL
V
t
CC
FVL
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