XC3090A-6PC84C Xilinx Inc, XC3090A-6PC84C Datasheet - Page 14
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XC3090A-6PC84C
Manufacturer Part Number
XC3090A-6PC84C
Description
FPGA XC3000 Family 6K Gates 320 Cells 135MHz CMOS Technology 5V 84-Pin PLCC
Manufacturer
Xilinx Inc
Datasheet
1.XC3090A-6PC84C.pdf
(76 pages)
Specifications of XC3090A-6PC84C
Package
84PLCC
Family Name
XC3000
Device Logic Units
320
Device System Gates
6000
Number Of Registers
928
Maximum Internal Frequency
135 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
70
Ram Bits
64160
Re-programmability Support
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC3000 Series Field Programmable Gate Arrays
7-16
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area.
Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two
non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
V
CC
KEEPER CIRCUIT
D
A
WEAK
D
A
A
D
B
D
B
B
Z
Z = D
=
D
A
A
• D
D
•
C
B
A
• D
+
C
D
•
B
...
•
D
• D
B
C
C
N
+ D
C
•
C
+
… +
D
N
•
November 9, 1998 (Version 3.1)
(LOW)
D
N
N
D
N
N
X3036
X1741A
V
CC
R