XC3042A-7TQ144C Xilinx Inc, XC3042A-7TQ144C Datasheet - Page 51

• Manufacturer Part Number: XC3042A-7TQ144C
• Description: FPGA XC3000 Family 3K Gates 144 Cells 113MHz CMOS Technology 5V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3042A-7TQ144C

• Package: 144TQFP
• Family Name: XC3000
• Device System Gates: 3000
• Number Of Registers: 480
• Maximum Internal Frequency: 113 MHz
• Typical Operating Supply Voltage: 5 V
• Ram Bits: 30784
• Re-programmability Support: Yes
• Case: TQFP144
• Dc: 95+

XC3100A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100A Operating Conditions
Note:
XC3100A DC Characteristics Over Operating Conditions
Notes:
November 9, 1998 (Version 3.1)
Symbol
Symbol
V
V
I
V
V
V
V
V
V
V
V
I
CCPD
I
CCO
C
T
RLL
RIN
I
IHT
IHC
CC
ILT
ILC
OH
OH
OL
OL
IL
IN
IN
1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for
3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
device configured with a tie option.
the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 package.
R
Supply voltage relative to GND Commercial 0 C to +85 C junction
Supply voltage relative to GND Industrial -40 C to +100 C junction
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
High-level output voltage (@ I
Low-level output voltage (@ I
High-level output voltage (@ I
Low-level output voltage (@ I
Power-down supply voltage (PWRDWN must be Low)
Quiescent LCA supply current in addition to I
Input Leakage Current
Input capacitance, all packages except PGA175
Input capacitance, PGA 175
Pad pull-up (when selected) @ V
Horizontal Longline pull-up (when selected) @ logic Low
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Description
OL
OL
Description
OH
OH
= 8.0 mA, V
= 8.0 mA, V
= –8.0 mA, V
= –8.0 mA, V
IN
= 0 V
3
XC3000 Series Field Programmable Gate Arrays
CC
CC
CCPD
CC
CC
min)
min)
min)
min)
1
Commercial
Industrial
4.25
70%
Min
4.5
2.0
0
0
3.86
3.76
2.30
0.02
0.20
Min
–10
CC
or GND, and the LCA
100%
5.25
20%
Max
V
250
5.5
0.8
Max
0.40
0.40
0.17
2.80
+10
CC
14
10
15
15
20
8
Units
Units
V
V
mA
mA
mA
mA
ns
pF
pF
pF
pF
V
V
V
V
CC
CC
V
V
V
V
V
A
7-53
7