DS90C383MTDX National Semiconductor, DS90C383MTDX Datasheet - Page 15

• Manufacturer Part Number: DS90C383MTDX
• Description: LVDS Flat Panel Display 0.45V 56-Pin TSSOP T/R
• Manufacturer: National Semiconductor

Specifications of DS90C383MTDX

• Package: 56TSSOP
• Number Of Elements Per Chip: 4
• Transmission Data Rate: 1800 Mbps
• Differential Input Low Threshold Voltage: -0.1 V
• Differential Input High Threshold Voltage: 0.1 V
• Typical Operating Supply Voltage: 3.3 V

RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter
G : Ground
I : Input
O : Output
P : Power
NC : No Connect
DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver
DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver
CC
CC
Pin Name
Pin Name
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
CC
CC
CC
CC
I/O
I/O
(Continued)
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TxIN21
TxIN23
TxIN11
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
TxIN9
By Pin
VCC
No.
No.
28
28
4
4
1
1
1
1
4
5
1
2
1
3
4
4
1
1
1
1
4
5
1
2
2
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
P
I
I
I
I
I
I
I
I
I
15
Description
Description
C7
E1
E6
H2
B8
C2
C3
F2
F3
F6
By Pin Type
PLL VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
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P
P
P
P