W9864G2GH-6 Winbond Electronics, W9864G2GH-6 Datasheet
W9864G2GH-6
Specifications of W9864G2GH-6
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W9864G2GH-6 Summary of contents
Page 1
... Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 8.1 Simplified Stated Diagram ............................................................................................ 13 9. ELECTRICAL CHARACTERISTICS......................................................................................... 14 9.1 Absolute Maximum Ratings .......................................................................................... 14 512K X 4 BANKS X 32BITS SDRAM Publication Release Date:May 13, 2008 - 1 - W9864G2GH Revision A11 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 41 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 41 11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 42 11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 43 12. PACKAGE SPECIFICATION .................................................................................................... 44 12.1 86L TSOP (II)-400 mil................................................................................................... 44 13. REVISION HISTORY ................................................................................................................ 45 W9864G2GH Publication Release Date:May 13, 2008 - 2 - Revision A11 ...
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... Interface: LVTTL • Packaged in TSOP II 86-pin , using Lead free materials with RoHS compliant 3. AVAILABLE PART NUMBER PART NUMBER W9864G2GH-5 200MHz/CL3 W9864G2GH-6 166MHz/CL3 W9864G2GH-6C 166MHz/CL3 W9864G2GH-6I 166MHz/CL3 W9864G2GH-7 133MHz/CL3 MAXIMUM SELF SPEED REFRESH CURRENT 2mA 2mA 2mA 2mA 2mA - 3 - W9864G2GH =7 ...
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... DQ6 VSSQ DQ7 NC VCC DQM0 WE CAS RAS CS NC BS0 BS1 A10/ DQM2 DQ16 V SS DQ17 DQ18 DQ19 DQ20 V SS DQ21 DQ22 V CC DQ23 W9864G2GH DQ15 DQ14 83 DQ13 DQ12 80 DQ11 DQ10 77 DQ9 DQ8 DQM1 CLK 68 CKE DQM3 DQ31 DQ30 54 DQ29 DQ28 51 DQ27 50 ...
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... Ground for input buffers and logic circuit inside Ground DRAM. Power for I/O Separated power from VCC, to improve DQ Buffer noise immunity. Ground for I/O Separated ground from VSS, to improve DQ Buffer noise immunity. No connection.(The NC pin must connect to No Connection ground or floating.) Publication Release Date:May 13, 2008 - 5 - W9864G2GH Revision A11 ...
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... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * W9864G2GH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ31 DQM0~3 COLUMN DECODER CELL ARRAY BANK #3 ...
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... Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. pins must be ramp up simultaneously to the specified voltage when ). The maximum time that each bank can be held active is RRD Publication Release Date:May 13, 2008 - 7 - W9864G2GH + 0.3V on VCC has RSC ). RC delay ...
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... Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. W9864G2GH Publication Release Date:May 13, 2008 - 8 - ...
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... Data Data Data Data Data BURST LENGTH (disturb address is A0) No address carry from (disturb addresses are A0 and A1) No address carry from (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS Publication Release Date:May 13, 2008 - 9 - W9864G2GH BURST LENGTH Revision A11 ...
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... AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. ) has been satisfied. Issue of Auto Data-in to Active delay (t DAL DAL (min). RAS - 10 - W9864G2GH and When using the Auto Publication Release Date:May 13, 2008 ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. W9864G2GH . The input buffers need (min ...
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... These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. TABLE 1 TRUTH TABLE (NOTE (1), (2)) CKEn DQM BS0 W9864G2GH RAS CAS A10 A0- ...
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... REF IDLE Power Down CKE Active ROW Power ACTIVE Down CKE Read CKE Read WRITE READ Write CKE READA WRITEA Precharge Precharge - 13 - W9864G2GH CBR Refresh READ SUSPEND CKE READA SUSPEND CKE Automatic sequence Manual input Publication Release Date:May 13, 2008 Revision A11 ...
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... VCC 2.7 - VCC Q 2.3 2.5 VCC VCC 2 -0 0.8* - VCC -0 2 -10 - I(L) I -10 - o(L) Publication Release Date:May 13, 2008 - 14 - W9864G2GH UNIT NOTES °C 1 °C 1 °C 1 ° MAX. UNIT NOTES 3.6 V 3.6 V 3.6 V 3.6 V 2.7 V 2 VCC +0 +0 VCC 0. VCC -2mA OH 0.4 ...
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... VCC = 3.3V±0.3V for - SYM. -5 -6/-6C/-6I I 110 CC1 I 40 CC2 CC2P I 15 CC2S CC2PS CC3 CC3P I 150 CC4 I 170 CC5 I 2 CC6 - 15 - W9864G2GH SYM. MIN. MAX. UNIT CLK -40 ° ~85 ° MAX. UNIT NOTES -7 100 ...
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... DS 1.0 1 1.5 1.5 AS 1.0 1 1.5 1.5 CKS 1.0 1.0 t CKH -- -- t 1.5 1.5 CMS 1.0 1.0 t CMH -- -- REF RSC XSR - 16 - W9864G2GH = -40 ° ~85 ° C) (Notes: A -6C -7 UNIT NOTES MIN. MAX. MIN. MAX 100000 45 100000 7.5 1000 10 1000 6 1000 7 1000 10 1000 -- -- 5 5.5 ...
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... Input Signal T Input Reference Level Input Reference Level (-6C, VCC/VCCQ=2.3V~2.7V) output ohms AC TEST LOAD ( 1.4V 50 ohms output 30pF - 17 - W9864G2GH CONDITIONS 1.4V 1.2V See diagram below 1/1 nS 1.4V 1.2V (-6C, VCC/VCCQ=2.3V∼2.7V) 1.2V 50 ohms ohms 30pF AC TEST LOAD (2) Publication Release Date:May 13, 2008 Revision A11 ...
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... If tr & longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter t ( The maximum can’t be more than 10nS for low frequency application 10. If clock rising time ( longer than 1nS 1nS. T /2-0.5)nS should be added to the parameter. T Publication Release Date:May 13, 2008 - 18 - W9864G2GH (min.). IH (max.). ...
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... TIMING WAVEFORMS 10.1 Command Input Timing V IH CLK RAS CAS WE A0-A10 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKS t CKS Publication Release Date:May 13, 2008 - 19 - W9864G2GH CMH CMS t CKH Revision A11 ...
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... Read Timing CLK CS RAS CAS WE A0-A10 BS0 Read Command Read CAS Latency Valid Data-Out Publication Release Date:May 13, 2008 - 20 - W9864G2GH Valid Data-Out Burst Length Revision A11 ...
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... DH DS Valid Valid Data-in Data- CKS CKH CKS Valid Data-in Data- Valid Data-in Data- Valid Data-in Data- Valid Data-in Data- W9864G2GH t t CMH CMS Valid Valid Data-in Data- Valid Data- Valid Valid Data-in Data- Valid Valid Data-in Data-in *DQM2,3="L" Valid ...
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... Data-Out Valid Valid Data-Out Data-Out CKS CKH CKS Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out - 22 - W9864G2GH OPEN Valid Data-Out OPEN Valid Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out *DQM2,3="L" ...
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... RAS t t CMS CMH CAS t t CMS CMH A0-A10 Register set data BS0 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency "0" (Test Mode) A8 "0" Reserved Write Mode A10 "0" BS0 A0 Reserved "0" BS1 "0" W9864G2GH t RSC A0 Burst Length Sequential Reserved ...
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... RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 bx2 t t RRD RRD Precharge Active Precharge Active Read - 24 - W9864G2GH RAS RAS t RCD RBd RAe CAy RAe RBd CBz bx3 cy2 cy1 cy3 cy0 t RRD ...
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... MHz RAS t RCD t RCD RAc CAy CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t t RRD Read AP* Active Read AP W9864G2GH RAS RAS t RCD RAe RBd CBz RAe RBd cy3 bx2 bx3 cy0 cy1 cy2 dz0 t RRD RRD AP* Active Read ...
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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 t RRD Precharge Active Read - 26 - W9864G2GH RAS t RCD RAc RAc CAz t AC by4 by5 by6 by7 CZ0 Active Read Precharge Publication Release Date:May 13, 2008 Revision A11 ...
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... RAS RCD RBb RBb CBy t CAC ax3 ax4 ax0 ax1 ax2 ax5 ax6 ax7 by0 t RRD AP* Active Read * AP is the internal precharge start timing - 27 - W9864G2GH RAS t RCD RAc RAc CAz t CAC t CAC by1 by4 by5 by6 CZ0 Active Read AP* ...
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... MHz RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write - 28 - W9864G2GH RAS t RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 Active Write Precharge Publication Release Date:May 13, 2008 Revision A11 23 CZ2 ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 by3 t RRD AP* Active Write * AP is the internal precharge start timing - 29 - W9864G2GH RAS t RCD RAb CAz RAc by5 by4 by6 by7 CZ0 CZ1 CZ2 Write Active AP* Publication Release Date:May 13, 2008 ...
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... CCD CCD CCD t RAS t RAS t RCD CBx CAy CAm bx0 Ay0 Ay1 Ay2 a2 bx1 Read Read Read * AP is the internal precharge start timing - 30 - W9864G2GH CBz am1 am2 bz0 bz1 bz2 bz3 am0 Precharge Read AP* Publication Release Date:May 13, 2008 Revision A11 23 ...
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... CAS WE BS0 BS1 t RCD A10 RAa A0-A9 RAa CAx DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank # RAS CAy ax5 ay1 ax0 ax1 ax3 ay0 ax2 ax4 Write - 31 - W9864G2GH ay2 ay4 ay3 D D Precharge Publication Release Date:May 13, 2008 Revision A11 ...
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... DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active Read * AP is the internal precharge start timing - 32 - W9864G2GH RAS CAx t AC bx1 bx2 bx3 bx0 AP* Publication Release Date:May 13, 2008 Revision A11 ...
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... CKE DQ aw0 aw1 Active Bank #0 Write Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz RCD RAb RAb CAx bx0 aw2 aw3 AP* Active Write * AP is the internal precharge start - 33 - W9864G2GH RAS RP RAc RAc bx1 bx3 bx2 AP* Active Publication Release Date:May 13, 2008 Revision A11 ...
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... Auto Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W9864G2GH Auto Refresh (Arbitrary Cycle) Publication Release Date:May 13, 2008 Revision A11 ...
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... CLK RAS CAS WE BS0,1 A10 A0-A9 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS Self Refresh Cycle No Operation / Command Inhibit Self Refresh Exit - 35 - W9864G2GH CKS t XSR Arbitrary Cycle Publication Release Date:May 13, 2008 Revision A11 ...
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... A10 RBa A0-A9 RBa CBv DQM CKE t DQ Read Active Bank #0 Bank #1 Bank #2 Idle Bank # CBw CBx CBy AC av0 av1 av3 aw0 ax0 ay0 av2 Single Write - 36 - W9864G2GH CBz t AC az0 az1 az2 az3 Read Publication Release Date:May 13, 2008 Revision A11 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data CAa t CKS ax0 ax1 ax2 ax3 Read Precharge - 37 - W9864G2GH RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode Publication Release Date:May 13, 2008 Revision A11 ...
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... Act tRP AP Act tWR tRP AP tWR tRP represents the Write with Auto precharge command. represents the start of internal precharing. represents the Bank Active command W9864G2GH Act tWR tRP Act AP Act Act tWR tRP Publication Release Date:May 13, 2008 Revision A11 ...
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... Act Act Act Act Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W9864G2GH Act Act AP Act (min). RAS Publication Release Date:May 13, 2008 Revision A11 ...
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... In the case of Burst Length (1) CAS Latency=2 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM D0 DQ (2) CAS Latency=3 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM Read Write Read Write Read Write Read Write Read Read Read Q0 Q1 Read W9864G2GH Publication Release Date:May 13, 2008 Revision A11 ...
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... CAS latency =3 Read Command DQ (2) Write cycle (a) CAS latency =2 Write Command DQM Q0 DQ (b) CAS latency =3 Write Command DQM BST BST BST Note: BST represents the Burst stop command PRCG PRCG PRCG tWR PRCG tWR W9864G2GH Publication Release Date:May 13, 2008 Revision A11 ...
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... CKE/DQM Input Timing (Write Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK CKE MASK ( CKE MASK ( W9864G2GH CKE MASK Publication Release Date:May 13, 2008 Revision A11 ...
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... CKE/DQM Input Timing (Read Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM Open ( W9864G2GH Open Open Publication Release Date:May 13, 2008 Revision A11 ...
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... E 0.50 0.020 0.40 0.50 0.60 0.016 0.020 0.024 0.80 0.032 0.004 0.10 0.61 0.024 - 44 - W9864G2GH MAX. Publication Release Date:May 13, 2008 Revision A11 ...
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... Change -7 grade power supply voltage from 2.7V~3.6V 3,14,15,16 2.6V~3.6V Change power supply voltage -6C grade from 3,14,15,16, 3.0V~3.6V to 2.7V~3.6V, -7 grade from 2.6V~3. 2.7V~3.6V Important Notice - 45 - W9864G2GH DESCRIPTION & Transition Time of CLK CC5 AC test condition and calculate T Publication Release Date:May 13, 2008 Revision A11 ...