CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 54

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

2.0 Architecture Overview
2.6 Burst FIFO Buffers
2.5.7 ABR Flow Control Manager
2-20
The ABR Flow Control Manager operates in conjunction with the xBR Scheduler
to control the rate of ABR channels. The CN8237 implements the TM 4.1
specification in a template-controlled hardware state machine. Mindspeed
provides an initial set of templates which reside in SEG memory. The information
within these templates define conformant ABR behavioral responses to network
and connection states. The CN8237 generates ABR Source traffic, including
internally generated RM cells, according to the template instructions. The
reassembly coprocessor and the Flow Control Manager collaboratively act as a
fully compliant ABR Destination Terminal.
2.6 Burst FIFO Buffers
To conserve local memory bandwidth, the CN8237 does not use its local SRAM
as a buffer for incoming or outgoing data. Instead, the CN8237 uses six dedicated
internal FIFO buffers data as follows:
Figure 2-10
These templates provide three significant benefits to the user:
1.
2.
3.
•
•
• One FIFO buffer between the PHY interface and the segmentation coprocessor
•
Since they control the Flow Control Manager state machine, they can be
optimized for specific applications.
The programmability of the templates insulates the hardware from changes
in the relatively stable, yet immature, TM 4.1 specification.
Mindspeed provides the initial templates, which can be customized by the
user later, shortening developmen
Two DMA master burst FIFO buffers (read =16 words; write, 512 or 2 K
words, programmable via CONFIG1 bit 1).
Two DMA slave burst FIFO buffers, (read = 8 words and write = 64 words).
( 1 to 9 cells) . See
One FIFO buffer between the PHY interface and the reassembly coprocessor
(64 words).
Mindspeed Technologies
illustrates the data FIFO buffer.
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Section 4.2.4
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28237-DSH-001-C
CN8237