XC95288XL-10PQ208C Xilinx Inc, XC95288XL-10PQ208C Datasheet - Page 15

• Manufacturer Part Number: XC95288XL-10PQ208C
• Description: CPLD XC9500XL Family 6.4K Gates 288 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC95288XL-10PQ208C

• Package: 208PQFP
• Family Name: XC9500XL
• Device System Gates: 6400
• Number Of Macro Cells: 288
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 168
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Case: QFP

Detailed timing information may be derived from the full tim-
ing model shown in
DS054 (v2.5) May 22, 2009
Product Specification
T
PSU
R
Setup Time = T
T
T
T
Propagation Delay = T
T
GCK
GSR
GTS
IN
Figure
Combinatorial
P-Term Clock
Combinatorial
Logic
Logic
Path
(a)
16. The values and explanations
PSU
(c)
T
T
T
T
T
LOGILP
PD
Clock to Out Time = T
PTCK
PTSR
PTTS
LOGI
D/T Q
Figure 16: Detailed Timing Model
Figure 15: Basic Timing Model
S*T
T
PTA
www.xilinx.com
PCO
PCO
D/T
CE
for each parameter are given in the individual device data
sheets.
XC9500XL High-Performance CPLD Family Data Sheet
T
T
SUI
HI
T
T
T
SR
T
PDI
AOI
RAI
F
T
Macrocell
COI
Q
Setup Time = T
Internal System Cycle Time = T
Combinatorial
Combinatorial
Logic
Logic
T
SU
OUT
(b)
(d)
Clock to Out Time = T
D/T Q
T
D/T Q
SLEW
SYSTEM
DS054_15_042101
DS054_16_042101
T
CO
T
EN
CO
15