XC2V4000-4FF1152C Xilinx Inc, XC2V4000-4FF1152C Datasheet - Page 84

• Manufacturer Part Number: XC2V4000-4FF1152C
• Description: FPGA Virtex-II Family 4M Gates 51840 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V4000-4FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II
• Device Logic Units: 51840
• Device System Gates: 4000000
• Number Of Registers: 46080
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 824
• Ram Bits: 2211840
• Re-programmability Support: Yes
• Case: BGA
• Dc: 05+

Input Clock Tolerances
Table 39: Input Clock Tolerances
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
2.
3.
Input Clock Low/High Pulse Width
PSCLK
PSCLK and CLKIN
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
“DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
If both DLL and CLKFX outputs are used, follow the more restrictive specification.
If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within ±5% (45/55 to 55/45).
Description
R
(3)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
PSCLK_PULSE
PSCLK_PULSE and
CLKIN_PULSE
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL_HF
CLKIN_CYC_JITT_DLL_LF
CLKIN_PER_JITT_DLL_LF
CLKFB_DELAY_VAR_EXT
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX_HF
CLKIN_CYC_JITT_FX_LF
CLKIN_PER_JITT_FX_LF
Symbol
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< 1MHz
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
Virtex-II Platform FPGAs: DC and Switching Characteristics
Constraints
F
CLKIN
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
Min
-6
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
25.00
25.00
10.00
Speed Grade
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
Min
-5
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
Min
-4
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
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