XC95288XL-10FG256C Xilinx Inc, XC95288XL-10FG256C Datasheet - Page 11

• Manufacturer Part Number: XC95288XL-10FG256C
• Description: CPLD XC9500XL Family 6.4K Gates 288 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 256-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC95288XL-10FG256C

• Package: 256FBGA
• Family Name: XC9500XL
• Device System Gates: 6400
• Number Of Macro Cells: 288
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 192
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C

I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
The input buffer is compatible with 5V CMOS, 5V TTL, 3.3V
CMOS, and 2.5V CMOS signals. The input buffer uses the
internal 3.3V voltage supply (V
input thresholds are constant and do not vary with the
DS054 (v2.5) May 22, 2009
Product Specification
Macrocell
(Inversion in
AND-array)
R
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
Product Term OE
To FastCONNECT
Switch Matrix
CCINT
Figure 10: I/O Block and Output Enable Capability
Global OE 4
Global OE 3
Global OE 1
Global OE 2
) to ensure that the
PTOE
OUT
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buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See
details.
V
(50 mV typical) to help reduce system noise for input signals
with slow rise or fall edges.
XC9500XL High-Performance CPLD Family Data Sheet
CCIO
Macrocells
To other
voltage. Each input buffer provides input hysteresis
1
0
Available in XC95144XL
and XC95288XL
Slew Rate
Control
Programmable
Ground
User-
Bus-Hold
I/O Block
DS054_10_042101
I/O
Figure 10
for
11