954204BGLFT Integrated Device Technology (Idt), 954204BGLFT Datasheet - Page 13

• Manufacturer Part Number: 954204BGLFT
• Description: PLL Clock Synthesizer Dual 56-Pin TSSOP T/R
• Manufacturer: Integrated Device Technology (Idt)
• Type: PLL Clock Synthesizerr

Specifications of 954204BGLFT

• Package: 56TSSOP
• Number Of Elements Per Chip: 2
• Output Frequency Range: 33.33 to 400 MHz
• Operating Temperature: 0 to 70 °C
• Operating Supply Voltage: 3.3 V

0933D—03/16/05
Table 2: LCDCLK_SS Frequency Select
SMBus Table: Vendor & Revision ID Register
SMBus Table: Clock Request Control Register
SMBus Table: LCDCLK_SS Control Register
Byte9/
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 7
Byte 8
Byte 9
bit1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Integrated
Circuit
Systems, Inc.
17, 18
17, 18
17,18
32
32
32
33
33
33
Pin #
Pin #
Pin #
9
-
-
-
-
-
-
-
-
-
-
-
S3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LCDCLK_SS/SRCCLK0
*SEL SRC_LCDCLK#
LCDCLK_SS Spread
CLKREQ B# Control
CLKREQ B# Control
CLKREQ B# Control
CLKREQ A# Control
CLKREQ A# Control
CLKREQ A# Control
S2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LCDCLK_SS3
LCDCLK_SS2
LCDCLK_SS1
LCDCLK_SS0
Enable
Enable
Nam e
Nam e
Nam e
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
S1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LCDCLK_SS/SRCCLK0
SRCCLK3 is controlled
SRCCLK1 is controlled
SRCCLK2 is controlled
SRCCLK0 is controlled
SRCCLK5 is controlled
SRCCLK4 is controlled
Control Function
O utput Enable
REVISIO N ID
VENDO R ID
Pin 17/18
Enable SS
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
Control
Control
MHz
Select
Bit S3
Bit S2
Bit S1
Bit S0
13
Reserved
Reserved
Reserved
Spread % Spread Type
+/-1.25
+/-0.3
+/-0.5
+/-0.6
+/-0.8
+/-1.0
+/-1.5
+/-0.4
1.25
1.75
0.8
1.5
2.5
1
2
3
-
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
Center
Center
Center
Center
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Down
-
Not Controlled
Not Controlled
Not Controlled
Not Controlled
Not Controlled
Not Controlled
See LCDCLK_SS Frequency
Disable (HiZ)
LCDCLK
O FF
0
0
0
-
-
-
-
-
-
-
-
Select Table 2
Controlled
Controlled
Controlled
Controlled
Controlled
Controlled
SRCCLK0
Enable
O N
1
1
1
-
-
-
-
-
-
-
-
ICS954204
PWD
PWD
PWD
x
x
x
x
0
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
-
-
-