XC3195A-3PQ208C Xilinx Inc, XC3195A-3PQ208C Datasheet - Page 26

• Manufacturer Part Number: XC3195A-3PQ208C
• Description: FPGA XC3100A Family 7.5K Gates 484 Cells 270MHz CMOS Technology 5V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3195A-3PQ208C

• Package: 208PQFP
• Family Name: XC3100A
• Device Logic Units: 484
• Device System Gates: 7500
• Number Of Registers: 1320
• Maximum Internal Frequency: 270 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 176
• Ram Bits: 94944
• Re-programmability Support: Yes
• Case: QFP208
• Dc: 97+

XC3000 Series Field Programmable Gate Arrays
Notes: 1. At power-up, V
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
7-28
(output)
(output)
(output)
(output)
A0-A15
D0-D7
DOUT
RCLK
CCLK
RCLK
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V
non-monotonically rising V
after V
High.
CC
To address valid
To data setup
To data hold
RCLK High
RCLK Low
has reached 4.0 V (2.5 V for the XC3000L).
CC
must rise from 2.0 V to V
Description
CC
may require a >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
CC
min in less than 25 ms. If this is not possible, configuration can be delayed by
Address for Byte n
7 CCLKs
1
2
3
2 T
Byte
Symbol
DRC
T
T
T
T
T
DRC
RCD
RCH
RAC
RCL
Byte n - 1
D6
CC
Address for Byte n + 1
1 T
Min
600
4.0
November 9, 1998 (Version 3.1)
3 T
60
rise time of >100 ms, or a
0
0
CCLK
RAC
RCD
Max
200
D7
Units
X5380
ns
ns
ns
ns
s
R