MAX9595CTM+T Maxim Integrated Products, MAX9595CTM+T Datasheet - Page 15

• Manufacturer Part Number: MAX9595CTM+T
• Description: IC AUDIO/VIDEO SWIT DUAL 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX9595CTM+T

• Function: Audio/Video Switch
• Circuit: 2 x SCART
• Voltage Supply Source: Single, Dual Supply
• Voltage - Supply, Single/dual (±): 4.75 V ~ 5.25 V, ±11.4 V ~ 12.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To implement the zero-crossing function when switch-
ing audio signals, set the ZCD bit by loading register
00h through the I
is not already set). Then set the mute bit low by loading
register 00h. Next, wait for a sufficient period of time for
the audio signal to cross zero. This period is a function
of the audio signal path’s low-frequency 3dB corner
(f
a zero-crossing detect is 0.5kHz or 0.5ms.
Next, set the appropriate TV switches using register
01h. Finally, clear the mute bit (while leaving the ZCD
bit high) using register 00h. The MAX9595 switches the
signal out of mute at the next zero crossing.
To implement the zero-cross function for TV volume
changes, or for TV and phono volume bypass switch-
ing, simply ensure the ZCD bit in register 00h is set.
The TV channel volume control ranges from -56dB to
+6dB in 2dB steps. The VCR volume control settings
are programmable for -6dB, 0dB, and +6dB. These
gain levels are referenced to the application inputs,
where some dividers are present. With the ZCD bit set,
the TV volume control switches only at zero-crossings,
thus minimizing click noise. The TV outputs can bypass
the volume control. Likewise, the monaural output sig-
nal can be processed by the TV volume control or it
can bypass the volume control.
Figure 5. SDA and SCL Signal Timing Diagram
L3dB
SDA
SCL
Audio/Video Switch for Dual SCART Connector
). Thus, if f
t
HD,STA
START CONDITION
L3dB
2
C-compatible interface (if the ZCD bit
______________________________________________________________________________________
= 1kHz, the time period to wait for
t
LOW
t
R
t
SU,DAT
t
F
Volume Control
t
HD,DAT
t
SU,STA
REPEATED START CONDITION
The MAX9595 uses a simple 2-wire serial interface
requiring only two standard microprocessor port I/O
lines. The fast-mode I
allows communication at data rates up to 400kbps or
400kHz. Figure 5 shows the timing diagram of the sig-
nals on the 2-wire interface.
The two bus lines (SDA and SCL) must be at logic-high
when the bus is not in use. The MAX9595 is a slave
device and must be controlled by a master device.
Pullup resistors from the bus lines to the supply are
required when push-pull circuitry is not driving the
lines.
The logic level on the SDA line can only change when
the SCL line is low. The start and stop conditions occur
when SDA toggles low/high while the SCL line is high
(see Figure 5). Data on SDA must be stable for the
duration of the setup time (t
high. Data on SDA is sampled when SCL toggles high
with data on SDA stable for the duration of the hold
time (t
byte. A total of nine clock cycles are required to trans-
fer a byte to the MAX9595. The device acknowledges
the successful receipt of the byte by pulling the SDA
line low during the 9th clock cycle.
HD,DAT
t
HD,STA
). Note that data is transmitted in an 8-bit
2
C-compatible serial interface
t
SU,STA
SU,DAT
STOP CONDITION
) before SCL goes
Digital Section
Serial Interface
t
BUF
15