LFEC1E-4TN144I Lattice, LFEC1E-4TN144I Datasheet - Page 12
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LFEC1E-4TN144I
Manufacturer Part Number
LFEC1E-4TN144I
Description
IC FPGA 1.5KLUTS 144TQFP
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC1E-4TN144I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC1E-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).
There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the
sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
1. Smaller devices have fewer PLL related lines.
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
Secondary Clock
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Primary Clock
4 Secondary Clocks per Quadrant
Routing
GND
DCS
2-9
LatticeECP/EC Family Data Sheet
Clock to
each slice
DCS
1
Architecture
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