LFXP3E-4TN144I Lattice, LFXP3E-4TN144I Datasheet - Page 11

• Manufacturer Part Number: LFXP3E-4TN144I
• Description: IC FPGA 3.1KLUTS 144TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
Clock Input
From Routing
From Routing
From Routing
From Routing
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
Clock
Clock
Input
Input
DCS
2-8
2
Routing
Routing
From
From
Routing
Routing
From
From
LatticeXP Family Data Sheet
DCS
2
1
From Routing
From Routing
From Routing
From Routing
Clock Input
Architecture