LFXP15E-3FN388C Lattice, LFXP15E-3FN388C Datasheet - Page 17
LFXP15E-3FN388C
Manufacturer Part Number
LFXP15E-3FN388C
Description
IC FPGA 15.4KLUTS 388FPBGA
Manufacturer
Lattice
Datasheet
1.LFXP6C-3TN144C.pdf
(130 pages)
Specifications of LFXP15E-3FN388C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP15E-3FN388C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 17 of 130
- Download datasheet (779Kb)
Lattice Semiconductor
Figure 2-15. Memory Core Reset
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-14
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeXP Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture
Related parts for LFXP15E-3FN388C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.2V -3 S pd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 268 IO 1. 2V -3 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.2V -3 S pd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 188 IO 1. 2V -3 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 268 IO 1. 2V -3 Spd
Manufacturer:
Lattice
Part Number:
Description:
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.4KLUTS 484FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.4KLUTS 256FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.4KLUTS 388FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.4KLUTS 388FPBGA
Manufacturer:
Lattice
Datasheet: