LFSC3GA15E-5FN900I Lattice, LFSC3GA15E-5FN900I Datasheet - Page 10

• Manufacturer Part Number: LFSC3GA15E-5FN900I
• Description: IC FPGA 15.2KLUTS 900FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-5FN900I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the LatticeSC devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU)
resources. The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal
directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
sysCLOCK Network
The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the
device: primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are
free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources
available to each slice.
Figure 2-4. Slice Clock Selection
Primary Clock Sources
LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the
following:
• Primary clock input pins
• Edge clock input pins
• Two outputs per DLL
MUX 16x1 x 1
MUX 2x1 x 8
MUX 4x1 x 4
MUX 8x1 x 2
LUT 4x8 or
LUT 5x4 or
LUT 6x2 or
LUT 7x1 or
Logic
Secondary Clock
Note: GND is available to switch off the network.
Primary Clock
Routing
GND
2-bit Counter x 4
2-bit Comp x 4
2-bit Add x 4
2-bit Sub x 4
Ripple
12
6
2-6
SPR 16x2 x 4
DPR 16x2 x 2
SPR 16x4 x 2
DPR 16x4 x 1
SPR 16x8 x 1
RAM
Clock to Slice
LatticeSC/M Family Data Sheet
ROM 16x1 x 8
ROM 16x2 x 4
ROM 16x4 x 2
ROM 16x8 x1
ROM
Architecture