LFSC3GA25E-6FN900C Lattice, LFSC3GA25E-6FN900C Datasheet - Page 23
LFSC3GA25E-6FN900C
Manufacturer Part Number
LFSC3GA25E-6FN900C
Description
IC FPGA 25.4KLUTS 900FPBGA
Manufacturer
Lattice
Datasheet
1.LFSC3GA15E-5FN256C.pdf
(237 pages)
Specifications of LFSC3GA25E-6FN900C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFSC3GA25E-6FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-20. Input Register Block
PURESPEED
I/O Buffer)
(from
DI
1. UPDATE, Set and Reset not shown for clarity
2. Adaptive input logic is only available in selected PIO
3. By four shift modes utilize DDR/shift register block from paired PIO.
4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to
disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used
to disable any/all input signals to save power.
Delay
Block
1
Latch
Adaptive
CLKENABLE
Optional
Logic
Input
2
2-19
• DDR
• DDR + half clock
• DDR + shift x1
• DDR + shift x2
• DDR + shift x4
• Shift x1
• Shift x2
• Shift x4
DDR/Shift Register Block
SDR Register/Latch Block
D-Type/
3
Latch
CLKDISABLE
3
LatticeSC/M Family Data Sheet
IPOS0
IPOS1
INEG0
INEG1
LCLKIN (ECLK/SCLK)
HCLKIN (ECLK/SCLK)
DCNTL[0:8]
(From DLL)
INDD
INCK
INFF
LOCK
RUNAIL
Routing
To
Architecture
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