LFE2M100SE-7FN900C Lattice, LFE2M100SE-7FN900C Datasheet - Page 126
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LFE2M100SE-7FN900C
Manufacturer Part Number
LFE2M100SE-7FN900C
Description
IC FPGA 95KLUTS 900FPBGA
Manufacturer
Lattice
Datasheet
1.LFE2M100SE-5FN900C.pdf
(386 pages)
Specifications of LFE2M100SE-7FN900C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M100SE-7FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one
connection with a package ball or pin.
Number
Pin
136
137
138
139
140
141
142
143
144
Function
Pin/Pad
VCCAUX
VCCIO0
PT6B
PT6A
PT4B
PT4A
PT2B
PT2A
GND
Bank
LFE2-6E/SE
0
0
0
0
0
0
0
-
-
Dual Function
VREF2_0
VREF1_0
Differential
4-25
C
C
C
T
T
T
Function
Pin/Pad
VCCAUX
VCCIO0
PT16B
PT16A
PT6B
PT6A
PT2B
PT2A
GND
LatticeECP2/M Family Data Sheet
Bank
0
0
0
0
0
0
0
-
-
LFE2-12E/12SE
Function
VREF2_0
VREF1_0
Dual
Pinout Information
Differential
C
C
C
T
T
T
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