STM8L151F3U6 STMicroelectronics, STM8L151F3U6 Datasheet - Page 96
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STM8L151F3U6
Manufacturer Part Number
STM8L151F3U6
Description
MCU 8BIT 8KB FLASH 20-UFQFPN
Manufacturer
STMicroelectronics
Series
STM8L EnergyLiter
Datasheet
1.STM8L151G3U6.pdf
(110 pages)
Specifications of STM8L151F3U6
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, IR, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-UFQFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11495-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8L151F3U6
Manufacturer:
ST
Quantity:
2 000
Part Number:
STM8L151F3U6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
STM8L151F3U6TR
Manufacturer:
TI
Quantity:
1 530
Company:
Part Number:
STM8L151F3U6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical parameters
7.4
96/110
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
Table 52.
1. Data based on characterization results, not tested in production.
Static latch-up
●
Table 53.
Thermal characteristics
The maximum chip junction temperature (T
Table 14: General operating conditions on page
The maximum chip-junction temperature, T
the following equation:
Where:
●
●
●
●
●
V
V
Symbol
ESD(HBM)
ESD(CDM)
LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
T
Θ
P
P
internal power.
P
Where:
P
Amax
JA
Dmax
INTmax
I/Omax
I/Omax
Symbol
is the package junction-to-ambient thermal resistance in ° C/W
LU
is the maximum ambient temperature in ° C
is the sum of P
ESD absolute maximum ratings
Electrical sensitivities
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
= Σ (V
represents the maximum power dissipation on output pins
is the product of I
OL
*I
Static latch-up class
OL
Ratings
) + Σ((V
INTmax
Doc ID 018780 Rev 2
DD
T
Jmax
DD
and P
and V
-V
= T
Parameter
OH
I/Omax
DD
Amax
)*I
, expressed in Watts. This is the maximum chip
Jmax
Jmax
OH
+ (P
(P
),
, in degree Celsius, may be calculated using
) must never exceed the values given in
52.
Dmax
Dmax
Conditions
T
A
= P
= +25 °C
x Θ
INTmax
JA
)
STM8L151x2, STM8L151x3
+ P
I/Omax
Maximum
value
)
2000
Class
500
II
(1)
Unit
V