NUC140RE3CN Nuvoton Technology Corporation of America, NUC140RE3CN Datasheet - Page 287
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NUC140RE3CN
Manufacturer Part Number
NUC140RE3CN
Description
IC MCU 32BIT 128KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Specifications of NUC140RE3CN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC140RE3CN
Manufacturer:
PANASONIC
Quantity:
40 000
Company:
Part Number:
NUC140RE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC140RE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
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5.9.5
start automatically after a user-specified suspending interval.
If software does not update the SPI_TX0 register, the TX_EMPTY flag will be set to 1 after the 3
data transfer sequence is finished
The active state of slave select signal can be defined by the settings of SS_LVL bit (SPI_SSR[2])
and SS_LTRIG bit (SPI_SSR[4]). The serial clock (SPICLK) idle state can be configured as high
state or low state by setting the CLKP bit (SPI_CNTRL[11]). It also provides the bit length of a
transaction word in TX_BIT_LEN (SPI_CNTRL[7:3]), the transfer number in TX_NUM
(SPI_CNTRL[8]), and transmit/receive data from MSB or LSB first in LSB bit (SPI_CNTRL[10]).
Users also can select which edge of serial clock to transmit/receive data in TX_NEG/RX_NEG
(SPI_CNTRL[2:1]) registers. Four SPI timing diagrams for master/slave operations and the
related settings are shown as below.
SPICLK
SPISS
Timing Diagram
MOSI
MISO
Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=0, CNTRL[TX_NUM]=0x0, CNTRL[TX_BIT_LEN]=0x08
NuMicro™ NUC130/NUC140 Technical Reference Manual
SS_LVL=1
SS_LVL=0
CLKP=0
CLKP=1
1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0 or
2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1
TX0[7]
RX0[7]
MSB
MSB
Figure 5-60 SPI Timing in Master Mode
RX0[6]
TX0[6]
RX0[5]
TX0[5]
- 287 -
RX0[4]
TX0[4]
Publication Release Date: June 14, 2011
RX0[3]
TX0[3]
RX0[2]
TX0[2]
RX0[1]
TX0[1]
Revision V2.01
RX0[0]
TX0[0]
LSB
LSB
rd
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