NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 328

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.11.5 Register Description
Watchdog Timer Control Register (WTCR)
Register
WTCR
Note: All bits can be write in this register are write-protected. To program it needs to write “59h”, “16h”, “88h” to address
0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
Bits
[31]
[30:11]
[10:8]
DBGACK_W
WTE
DT
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
WDT_BA+0x00
Descriptions
DBGACK_WDT
Reserved
WTIS
WTIE
30
22
14
6
Reserved
WTWKF
R/W
R/W
29
21
13
5
Watchdog Timer counter will keep going no matter ICE debug mode
acknowledged or not.
Reserved
Watchdog Timer Interval Select (write-protection bits)
These three bits select the timeout interval for the Watchdog timer.
ICE debug mode acknowledge Disable (write-protection bit)
0 = ICE debug mode acknowledgement effects Watchdog Timer counting.
Watchdog Timer counter will be held while ICE debug mode acknowledged.
1 = ICE debug mode acknowledgement disabled.
Description
Watchdog Timer Control Register
WTIS
000
001
010
011
100
WTWKE
28
20
12
Timeout Interval
4
- 328 -
2
2
Reserved
Selection
2
2
2
10
12
4
6
8
* T
* T
* T
* T
* T
WDT
WDT
WDT
WDT
WDT
Reserved
WTIF
27
19
11
3
Publication Release Date: June 14, 2011
(2
(2
(2
(2
(2
Interrupt Period
10
12
4
6
8
+ 1024) * T
+ 1024) * T
+ 1024) * T
+ 1024) * T
+ 1024) * T
WTRF
26
18
10
2
WDT
WDT
WDT
WDT
WDT
WTR Timeout Interval
102.4 ms ~ 204.8 ms
(WDT_CLK=10 kHz)
409.6 ms ~ 512 ms
6.4 ms ~ 108.8 ms
25.6 ms ~ 128 ms
1.6 ms ~ 104 ms
WTRE
WTIS
25
17
9
1
Revision V2.01
Reset Value
0x0000_0700
WTR
24
16
8
0