SAF-XC164CS-16F40FBB Infineon Technologies, SAF-XC164CS-16F40FBB Datasheet - Page 66

• Manufacturer Part Number: SAF-XC164CS-16F40FBB
• Manufacturer: Infineon Technologies

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive
For a period of N × TCM the accumulated PLL jitter is defined by the deviation D
D
So, for a period of 3 TCMs @ 20 MHz and K = 12: D
This formula is applicable for K × N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: D
Figure 16
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Data Sheet
N
[ns] = ±(1.5 + 6.32 × N /
selecting the maximum possible output prescaler factor K.
Acc. jitter
±8
±7
±6
±5
±4
±3
±2
±1
ns
f
0
MC
Approximated Accumulated PLL Jitter
0
cycles (TCM).
1
10 MHz
40 MHz
D
N
K = 15
5
20 MHz
f
MC
K = 12
);
f
MC
K = 10
10
in [MHz], N = number of consecutive TCMs.
K = 8
64
K = 6 K = 5
15
Nmax
3
= ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
[ns] = ±(1.5 + 600 / (K ×
20
Electrical Parameters
25
MCD05566
f
MC
Derivatives
V2.3, 2006-08
. Therefore,
XC164CS
N
N
f
MC
:
)).