NCP3170AGEVB ON Semiconductor, NCP3170AGEVB Datasheet - Page 11

• Manufacturer Part Number: NCP3170AGEVB
• Description: BOARD EVALUATION NCP3170ADR2G
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP3170AGEVB

• Design Resources: NCP3170 Schematic NCP3170AGEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 4.5 ~ 18 V
• Regulator Topology: Buck
• Frequency - Switching: 500kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP3170
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP3170AGEVBOS

logic by using the configuration below.
conjunction with the Power Good (PG) pin as shown in
Figure 33. The enable pin can either be tied to the output
voltage of the master voltage or tied to the input voltage with
a resistor to the PG pin of the master regulator.
slewed from ground to the set point of 800 mV. The slewing
process occurs over a 4.5 ms period, reducing the current
draw from the upstream power source, reducing stress on
internal MOSFETS, and ensuring the output inductor does
not saturate during start−up.
Pre−Bias Start−up
discharge the output capacitors. The soft start begins with
the internal reference at ground. Both the high side switch
and low side switches are turned off. The internal reference
slowly raises and the OTA regulates the output voltage to the
divided reference voltage. In a pre−biased condition, the
voltage at the FB pin is higher than the internal reference
voltage, so the OTA will keep the COMP voltage at ground
potential. As the internal reference is slewed up, the COMP
Figure 33. Enable Two Converter Power Sequencing
The part can be enabled with standard TTL or high voltage
The enable can also be used for power sequencing in
4.5 V − 18 V
Once the part is enabled, the internal reference voltage is
When starting into a pre−bias load, the NCP3170 will not
4.5 V − 18 V
R1
LOG
R2
4.5 V − 18 V
Figure 32. Logic Turn−on
LOG
AGND
AGND
EN
PG
EN
VIN
VIN
NCP3170
NCP3170
C1
C1
LOG
IN
VSW
VSW
FB
FB
EN
AGND
VIN
NCP3170
http://onsemi.com
Vo1
Vo2
Vo2
Vo1
11
pin is held low until the FB pin voltage surpasses the internal
reference voltage, at which time the COMP pin is allowed
to respond to the OTA error signal. Since the bottom of the
PWM ramp is at 0.6 V there will be a slight delay between
the time the internal reference voltage passes the FB voltage
and when the part starts to switch. Once the COMP error
signal intersects with the bottom of the ramp, the high side
switch is turned on followed by the low side switch. After the
internal reference voltage has surpassed the FB voltage, soft
start proceeds normally without output voltage discharge.
Power Good
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figure 34. All comparator outputs are ignored
during the soft start sequence as soft start is regulated by the
OTA since false trips would be generated. Further, the PG
pin is held low until the comparators are evaluated. PG state
does not affect the switching of the converter. After the soft
start period has ended, if the feedback is below the reference
voltage of comparator 1 (V
considered operational undervoltage (OUV). The device
will indicate the under voltage situation by the PG pin
remaining low with a 100 kW pull−up resistance. When the
feedback pin voltage rises between the reference voltages of
comparator 1 and comparator 2 (0.726 < V
the output voltage is considered power good and the PG pin
is released. Finally, if the feedback voltage is greater than
comparator 2 (V
operational overvoltage (OOV). The OOV will be indicated
by the PG pin remaining low. A block diagram of the OOV
and OUV functionality as well as a graphical representation
of the PG pin functionality is shown in Figures 34
through 36.
The output voltage of the buck converter is monitored at
Hysteresis = 14 mV
Hysteresis = 14 mV
FB
800 mV
Figure 35. OOV and OUV Window
Figure 34. OOV and OUV System
FB
> 0.862), the output voltage is considered
862 mV
726 mV
+
−
Power Good
+
+
comp 2
−
−
comp 1
FB
OOV
OUV
< 0.726), the output is
Complete
SOFT
Start
FB
12 V
Voov = 862 mV
Vref = 0.8 V
Vouv = 726 mV
< 0.862), then
100kW
PG