NCP3125CRAGEVB ON Semiconductor, NCP3125CRAGEVB Datasheet - Page 18

• Manufacturer Part Number: NCP3125CRAGEVB
• Description: BOARD EVALUATION NCP3125 CERAMIC
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP3125CRAGEVB

• Design Resources: NCP3125 Schematic NCP3125CRAGEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 4A
• Voltage - Input: 4.5 ~ 13.2 V
• Regulator Topology: Buck
• Frequency - Switching: 350kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP3125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP3125CRAGEVBOS

22 mF with a crossover frequency of 35 kHz, the
compensation values for common output voltages can be
calculated as shown in Table 6:
Calculating Soft−Start Time
following equations can be used.
C
C
I
a regulated output voltage is t
C
C
D
I
t
V
SS
SS
SS
Table 6. COMPENSATION VALUES
V
(V)
P
C
P
C
ramp
12
12
12
12
12
12
12
Assuming an output capacitance of 470 mF in parallel with
To calculate the soft−start delay and soft−start time, the
The time the output voltage takes to increase from 0 V to
5
5
5
5
5
in
t
t
SSdelay
SS
7.45 ms +
2.51 ms +
+
V
(V)
0.8
1.2
1.5
1.8
2.5
3.3
5.0
0.8
1.2
1.5
1.8
2.5
out
C
+
P
) C
= Compensation pole capacitor
= Compensation capacitor
= Compensation pole capacitor
= Compensation capacitor
= Duty ratio
= Soft−start interval
= Peak−to−peak voltage of the ramp
= Soft−start current
= Soft−start current
C
L
(mF)
2.2
2.7
2.7
3.9
4.7
5.6
6.8
1.8
2.7
2.7
3.3
3.3
out
P
2.83 nF ) 80 nF
2.83 nF ) 80 nF
) C
C
I
SS
I
(kW)
C
SS
RF
20
20
20
20
20
20
20
20
20
20
20
X
D
10 mA
0.9 V
V
ss
(nF)
ramp
Cf
X
1
1
1
1
1
1
1
1
1
1
1
10 mA
as shown in Equation 46:
³
0.9 V
27.5%
(nF)
150
100
100
120
Cc
82
68
47
68
56
39
33
27
0.243
0.412
0.487
0.806
0.453
0.953
(kW)
1.07
1.96
1.15
1.82
1.4
1.5
Rc
1.1 V
(eq. 45)
(eq. 46)
http://onsemi.com
0.82
0.82
0.68
0.56
(nF)
5.6
2.7
2.7
1.8
1.5
1.2
Cp
1
1
18
to the bottom of the ramp is considered t
delay time is the addition of the current set delay and t
which in this case is 9 ms and 7.45 ms respectively, for a
total of 16.45 ms.
Calculating Input Inrush Current
charging and output charging. The input charging of a buck
stage is usually not controlled, and is limited only by the
input RC network, and the output impedance of the upstream
power stage. If the upstream power stage is a perfect voltage
source, then the input charge inrush current can be depicted
as shown in Figure 26 and calculated as:
The delay from the charging of the compensation network
The input inrush current has two distinct stages: input
Figure 26. Input Charge Inrush Current
Vcomp
Vout
I
ICinrush_PK
120 A +
IPK
Figure 25. Soft−Start Ramp
1 +
0.1
12
CIN
V
V
IN
ESR
900 mV
ssdelay
. The total
(eq. 47)
ssdelay
,