STEVAL-PCC010V2 STMicroelectronics, STEVAL-PCC010V2 Datasheet - Page 162

• Manufacturer Part Number: STEVAL-PCC010V2
• Description: BOARD EVAL FOR ST802RT1A
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-PCC010V2

• Design Resources: STEVAL-PCC010V2 BOM STEVAL-PCC010V2 Schematic
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: ST802RT1A, STM32F207
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11465

Revision history
162/163
Table 89.
22-Apr-2011
Date
Document revision history (continued)
(continued)
Revision
6
Changed t
t
bus AC waveforms and measurement
Added
updated
Updated V
characteristics.
Updated
Updated R
Updated t
Updated R typical value in
Updated
Modified FSMC_NOE waveform in
multiplexed SRAM/PSRAM/NOR read
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
AIV)
NWEH)
Synchronous multiplexed NOR/PSRAM read
Synchronous multiplexed PSRAM write
Synchronous non-multiplexed NOR/PSRAM read
Figure 61: Synchronous non-multiplexed PSRAM write
Changed t
t
modified t
Table
Updated note 2 in
Table
Modified t
waveforms for I/O space write
Modified FSMC_NCEx signal in
waveforms for read
write
memory read
common memory write access
Specified Full speed (FS) mode for
peripheral-only connection in FS mode
host-only connection in FS
f(SCK)
d(CLKH-NOEH)
, t
Doc ID 15818 Rev 6
d(CLKH-NOEH)
access,
74.
72,
, and updated data latency from 1 to 0 in
to t
Table 52: USB OTG FS DC electrical characteristics
Table 53: USB OTG FS electrical
Table 61: ADC characteristics
Table 66: Embedded internal reference
Table
f(SCL)
START
w(CLK)
h(NIOWR-D)
w(SCKH)
d(CLKH-NExH
DD
AIN
Figure 70: NAND controller waveforms for common
minimum value in
access, and
to t
equation. Updated
in
73, and
in
minimum value in
d(CLKL-NOEH)
d(CLKH-NExH
Table 47: I2C characteristics
Table 64: TS
to t
Table
to t
access,
in
w(SCLH)
d(CLKL-NOEH)
) to t
Figure 67: PC Card/CompactFlash controller
Table
67,
d(CLKL-NExH)
Figure 71: NAND controller waveforms for
Table 65: VBAT monitoring
mode.
Figure 69: NAND controller waveforms for
Table
, t
) to t
, t
74.
Changes
access.
w(SCKL)
characteristics.
d(CLKH-NWEH)
Table 57: Ethernet DC electrical
Figure 68: NAND controller
Table 63: DAC
d(CLKL-NExH)
68,
Table
, and t
Figure 54: Asynchronous non-
Figure 88: USB OTG HS
STM32F205xx, STM32F207xx
Table
circuit.
to t
waveforms. Shifted end of
, t
and R
and
timings,
71,
d(CLKH-AIV)
d(CLKH-NWEH)
w(SCLL)
characteristics.
Figure 89: USB OTG HS
69,
Table
timings,
AIN
to t
, t
and in
Figure 58:
d(CLKH-AIV)
Table
Figure 60:
characteristics.
, t
voltage.
d(CLKL-NWEH)
equation.
timings, and
72,
r(SCK)
to t
Figure 59:
70,
Figure 38: I2C
Table
characteristics.
to t
d(CLKL-AIV)
timings,
to t
Table
d(CLKL-
to t
r(SCL)
and
73, and
, and
d(CLKL-
71,
, and
,