ADV3000ASTZ-RL Analog Devices Inc, ADV3000ASTZ-RL Datasheet - Page 19

IC HDMI/DVI SWITCH 3.1 80LQFP

ADV3000ASTZ-RL

Manufacturer Part Number
ADV3000ASTZ-RL
Description
IC HDMI/DVI SWITCH 3.1 80LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV3000ASTZ-RL

Function
Switch
Circuit
1 x 3:1
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
3 V ~ 3.6 V
Current - Supply
110mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], and PP_OCL pins.
This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface. The state of
each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 18. Parallel Interface Register Map
Name
High Speed
Device Modes
Auxiliary
Device Modes
Receiver
Settings
Input
Termination
Pulse 1
Input
Termination
Pulse 2
Receive
Equalizer 1
Receive
Equalizer 2
Transmitter
Settings
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channels Enable Bit
Table 19. PP_EN Description
PP_EN
0
1
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 20. High Speed Switch Mode Mapping
PP_CH[1:0]
00
01
10
11
Description
High speed channels off, low power/standby mode
High speed channels on
O[3:0]
A[3:0]
B[3:0]
C[3:0]
Bit 7
0
0
PP_EQ
Description
High Speed Source A switched to output
High Speed Source B switched to output
High Speed Source C switched to output
Illegal Value
Bit 6
High speed
switch enable
PP_EN
Auxiliary
switch enable
1
0
0
PP_EQ
Source A and Source B input termination pulse-on-source switch select (termination always on)
Source C input termination pulse-on-source switch select (termination always on)
Bit 5
0
0
0
0
PP_EQ
Source A and Source B input equalization level select
Bit 4
0
0
0
0
PP_EQ
Source C input equalization level select
Rev. 0 | Page 19 of 28
Bit 3
0
0
0
0
PP_EQ
PP_EQ
Output pre-emphasis
PP_PE[1]
AUXILIARY DEVICE MODES REGISTER
The auxiliary (low speed) switch is always enabled when using
the parallel interface.
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mode Mapping
PP_CH[1:0]
00
01
10
11
level select
Bit 2
0
0
0
0
PP_EQ
PP_EQ
PP_PE[0]
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
Bit 1
PP_CH[1]
PP_CH[1]
0
0
PP_EQ
PP_EQ
Auxiliary switch source select
High speed source select
Illegal Value
Description
Auxiliary Source A switched
to output
Auxiliary Source B switched
to output
Auxiliary Source C switched
to output
Bit 0
PP_CH[0]
PP_CH[0]
Input termination
on/off select
(termination always on)
1
0
0
PP_EQ
PP_EQ
Output current level
select
PP_OCL
ADV3000

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