LMX2331UEVAL National Semiconductor, LMX2331UEVAL Datasheet - Page 35

• Manufacturer Part Number: LMX2331UEVAL
• Manufacturer: National Semiconductor

Specifications of LMX2331UEVAL

• Lead Free Status / Rohs Status: Not Compliant

Test Setups
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input impedance. The
IF input impedance and reference oscillator impedance set-
ups are very much similar. The same setup is used for the
LMX2330TMEB/ LMX2330SLEEB Evaluation Boards. Mea-
suring the device’s input impedance facilitates the design of
appropriate matching networks to match the PLL to the VCO,
or in more critical situations, to the characteristic impedance
of the printed circuit board (PCB) trace, to prevent undesired
transmission line effects.
Before the actual measurements are taken, the Network
Analyzer needs to be calibrated, i.e. the error coefficients
need to be calculated. Therefore, three standards will be
used to calculate these coefficients: an open, short and a
matched load. A 1-port calibration is implemented here.
To calculate the coefficients, the PLL chip is first removed
from the PCB. The Network Analyzer port is then connected
to the RF OUT connector of the evaluation board and the
desired operating frequency is set. The typical frequency
range selected for the LMX233xU device’s RF synthesizer is
from 100 MHz to 2500 MHz. The standards will be located
down the length of the RF OUT transmission line. The trans-
mission line adds electrical length and acts as an offset from
the reference plane of the Network Analyzer; therefore, it
(Continued)
LMX233xU f
IN
Impedance Test Setup
35
must be included in the calibration. Although not shown, 0 Ω
resistors are used to complete the RF OUT transmission line
(trace).
To implement an open standard, the end of the RF OUT
trace is simply left open. To implement a short standard, a 0
Ω resistor is placed at the end of the RF OUT transmission
line. Last of all, to implement a matched load standard, two
100 Ω resistors in parallel are placed at the end of the RF
OUT transmission line. The Network Analyzer calculates the
calibration coefficients based on the measured S
eters. With this all done, calibration is now complete.
The PLL chip is then placed on the PCB. A power supply is
connected to V
pin is tied to the ground plane. Alternatively, the OSC
can be tied to V
(f
still connected to RF OUT, the measured f
is displayed.
Note: The impedance of the reference oscillator is measured
when the oscillator buffer is powered up (PWDN RF Bit = 0
or PWDN IF Bit = 0), and when the oscillator buffer is
powered down (PWDN RF Bit = 1 and PWDN IF Bit = 1).
IN
RF) is AC coupled to ground. With the Network Analyzer
CC
CC
and swept from 2.7V to 5.5V. The OSC
. In this setup, the complementary input
IN
RF impedance
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param-
in
pin
in