IA3223-C-FU Silicon Laboratories Inc, IA3223-C-FU Datasheet
IA3223-C-FU
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IA3223-C-FU Summary of contents
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... IA3222/IA3223 EZ DAA™ Chipset with Analog Interface DESCRIPTION The IA3222 and IA3223 integrated V.92 (56K) capable Data Access Arrangement (DAA) chipset is suitable for worldwide telephone line interface requirements and standards. The patented IsoBridge eliminates the need for usual telecom isolation components, such as transformers or optocouplers ...
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... DC Termination (Voltage Drop vs. Loop Current) ........................................................................................................................5 AC Termination (Line Impedance Matching) ................................................................................................................................6 DTMF Dialing ...............................................................................................................................................................................6 Pulse Dialing ................................................................................................................................................................................6 Caller ID .......................................................................................................................................................................................6 Power-Down Mode.......................................................................................................................................................................6 PACKAGE PIN DEFINITIONS.....................................................................................................................................................7 IA3223 System Side (QSOP-16) ..................................................................................................................................................7 IA3223A System Side (QSOP-20) ...............................................................................................................................................8 IA3222A Line Side (SOIC-8) ........................................................................................................................................................9 IA3222B Line Side (MSOP-10) ....................................................................................................................................................9 ELECTRICAL SPECIFICATIONS..............................................................................................................................................10 Absolute Maximum Ratings........................................................................................................................................................10 Recommended Operating Conditions ........................................................................................................................................10 DC Characteristics ...
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... SURGES, ISOLATION AND EMC .............................................................................................................................................35 Safety Isolation and Differential Surges .....................................................................................................................................35 Power-Line Cross.......................................................................................................................................................................37 Common-Mode Noise from the Mains Supply............................................................................................................................38 EMC ...........................................................................................................................................................................................39 RF Susceptibility ........................................................................................................................................................................39 RETURN LOSS AND TRANS-HYBRID RETURN LOSS ..........................................................................................................40 PACKAGE INFORMATION .......................................................................................................................................................42 QSOP-16 and QSOP-20 Packages............................................................................................................................................42 MSOP-10 Package.....................................................................................................................................................................42 SOIC-8 Package (JEDEC Outline MS-012AA)...........................................................................................................................42 ORDERING INFORMATION......................................................................................................................................................43 IA3222/IA3223 3 ...
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... Figure 22: Transmit gain versus ACIN capacitor................................................................................................................................... 18 Figure 23: Application schematic .......................................................................................................................................................... 22 Figure 24: Application schematic for legacy TBR21 current-limit support .......................................................................................... 24 Figure 25: IA3222/3223 evaluation board .......................................................................................................................................... 26 Figure 26: IA3222/3223 evaluation board layout ............................................................................................................................... 27 Figure 27: Single-ended interface ......................................................................................................................................................... 29 Figure 28: Differential interface — without reference .......................................................................................................................... 29 Figure 29: Differential interface — with reference................................................................................................................................ 29 IA3222/IA3223 4 ...
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... The chipset implements high-voltage isolation barrier between the IA3223 codec and its IA3222 line-side device by means of its patented IsoBridge technology. Where typical designs use costly transformers, optocouplers or discrete high voltage capacitors, IsoBridge reduces the Bill of Materials total cost by embedding high voltage capacitors into the PCB ...
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... Loss and Trans-Hybrid Return Loss” for more details. DTMF Dialing DTMF dialing is synthesized and generated by the application; only a few parameters in the IA3223, such as the gain and maximum transmission level, need to be set prior to dialing. Pulse Dialing Pulse dialing is accomplished by going on hook and off hook repeatedly to generate the make and break pulses the system application’ ...
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... PACKAGE PIN DEFINITIONS Pin-type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output PU=weak internal pull-up resistor PD=weak internal pull-down resistor IA3223 System Side Pin Definitions Pin Number Pin Name 1 LineStat 2 SCLK 3 CS OUT OUT 8 ExtClk 9 C EXT2 10 C EXT1 11 AC REF 12 ICG ...
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... IA3223 System Side Pin Definitions Pin Number Pin Name 1 LineStat 2 SCLK 3 CS OUT OUT 8 ExtClk 9 RNG/PPU 10 LIU/ OfHk 13 C EXT2 14 C EXT1 15 AC REF 16 ICG ICR ICT Note: Refer to the section on line monitoring for a description of the Line-Status pin. IA3223A System Side (QSOP-20) ...
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... Device ground 10 Device supply, self regulated through hook-switch transistor V DD IA3222A Line Side (SOIC-8) TM interface for transmitter path TM interface for receiver path TM interface reference ground IA3222B Line Side (MSOP-10) TM interface for transmitter path TM interface for receiver path TM interface reference ground IA3222/IA3223 9 ...
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... V + 0.5 DD -100 100 mA 150 mA Min. Typ. -25 3.0 3 1.2 100 10 220 57 tdih tcssuf tdisu 0 (write DI3 DI2 IA3222/IA3223 º Max. Unit 85 ºC 3 100 % kΩ 200 pF 120 mA 130 83.333 kHz ∞ mW/ ºC pin. REF tcssur tcsh DI1 ...
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... CS# CS# Data in Data (read) Data out Data out Min. -10 0 Min. 67.2 tcdo tcdo Floating DO3 DO2 Figure 2: Serial interface read-cycle timing diagram IA3222/IA3223 Typ. Max. Unit 10 µA 240 mV 0 RMS 25 V RMS 30 V RMS 40 V RMS 1.50 1. kΩ ...
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... V , high gain setting PP DD 1kHz, 100 low gain setting PP DD 120Hz IA3222/IA3223 Min. Typ. Max. Unit -85 dBm - dBm -3 ...
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... LP[5:4]=11, 600Ω load with bootstrap, DTMF tones 300Hz - 3400Hz, DC coupled f > 3400Hz, DC coupled 1kHz, 100 high headroom PP DD 1kHz, 100 other headrooms > 3400Hz, DC coupled, high headroom f > 3400Hz, DC coupled, other headrooms f = 1000Hz 3000Hz IA3222/IA3223 Min. Typ. Max. Unit -82 dBm - 0.5 ±dB 0.5 ± ...
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... 20mA, no current limit, normal headroom 20mA, no current limit, high headroom 42mA, TBR21 current limit, normal headroom 50mA, TBR21 current limit, normal headroom DD TBR21 legacy mode 230 Ω feed IA3222/IA3223 Min. Typ. Max. Unit 2.47 V 130 170 210 mA 80 108 135 V ...
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... IA3222/IA3223 500 1000 1500 2000 2500 3000 Aus tralia, LP[5:4]=01 New Zealand, LP[5:4]=01 TBR21, LP[5:4]=01 Figure 4: Transmit gain with complex loads Receive gain versus frequency (Hz) 500 1000 1500 ...
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... Return loss (dB) w ith complex loads versus frequency (Hz 2600 3000 3400 200 600 Figure 14: Return loss for complex modes IA3222/IA3223 Snoop noise (dBV) versus DC voltage ( Low gain High gain Voltage vs. current, TBR21 current limit Voltage vs. current, TBR21 current limit Loop current (mA) TBR21 requirement 1000 ...
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... Hi hdrm, TH=3 Lo hdrm, TH=3 Figure 20: Transmitter-path PSR aliasing into audio band with IA3222/IA3223 1000 1500 2000 2500 3000 Aus tralia, LP[5:4]=01 New Zealand, LP[5:4]=01 TBR21, LP[5:4]=01 Current-sensor gain versus temperature - Temperature (°C) ...
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... Figure 22: Transmit gain versus ACIN capacitor IA3222/IA3223 Out-of-band frequencies aliased into the transmitter and receiver paths 100 1000 10000 Frequency (kHz) Tx out-of-band rejection Hybrid out-of-band rejection Receiver out-of-band spurs Receiver out-of-band spurs 100000 1000000 10000000 ...
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... Device powered down (Note) (Note) Cx required? IA3222A IA3222B (IA3222B only) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes IA3222/IA3223 D0 PWD LP2 REVID RTH0 LP F0 Reserved Reset state Low High Low Low Cx1 required? (IA3222B only) Yes Yes Yes ...
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... Off hook LP [Note 1] Line polarity On hook and off hook Notes: 1. This bit is multiplexed to a digital output pin of the IA3223A the on-hook state, LACT will become high if the line voltage change is at least 10 to 20V in either direction. Parallel-Pickup Threshold 0: least sensitive (reset state) 1 ...
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... An external clock can be used to synchronize an external codec with the DAA in order to avoid aliasing. Minimum Input Frequency (MHz) Maximum Input Frequency (MHz) 0.0672 (internal) 1.38 1.84 2.76 3.68 5.52 7.37 0.0576 IA3222/IA3223 0.0828 (internal) 2.0 2.667 4.0 5.333 8.0 10.667 0.08333 21 ...
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... APPLICATIONS Application Schematic IA3222B for worldwide telecom compliance Figure 23: Application schematic IA3222/IA3223 22 ...
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... Refer to the component discussion for more details. Note 4: C10 and C14 need to be NPO if V.90 modem performance is required. Otherwise more cost effective to use X7R ceramic capacitors. capacitors, drawn on PCB (Contact IAI for details.) IA3222/IA3223 23 ...
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... TBR21 current limit is no longer in force in Europe but may still be required for certain countries, e.g. Algeria, Bahrain, Croatia, Estonia, Ghana, Ivory Coast, Lebanon, Morocco and Turkey. This application is suitable for all other countries as well. Figure 24: Application schematic for legacy TBR21 current-limit support IA3222/IA3223 24 ...
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... This effect is less pronounced with components of larger size and higher voltage rating. Note 2: C10 and C14 need to be NPO if V.90 modem performance is required. Otherwise more cost effective to use X7R ceramic capacitors. capacitors, drawn on PCB (Contact IAI for details.) IA3222/IA3223 25 ...
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... Legacy TBR21 support is possible but not recommended since so few countries require it and the standard has been superseded. Current limiting is now obsolescent if not obsolete. In order to meet TBR21 current limit, a DAA needs to dissipate 2 W safely. In the IA3222/3223 application, about half of this power is dissipated in R3, R4, R10 and R11 and the other half in the NPN transistor. Figure 25: IA3222/3223 evaluation board IA3222/IA3223 26 ...
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... For optimal audio performance, minimize trace lengths between the System Side and its supply-decoupling capacitors. • Q2, Q3 and Q4 should be laid out with a lot of extra copper on both sides of the board with thermal vias in order to facilitate heat dissipation. Figure 26: IA3222/3223 evaluation board layout IA3222/IA3223 27 ...
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... All three pins TX, RX and ACREF may also be connected to codec using coupling capacitors. For the ACREF pin, a capacitor of at least 100nF is recommended. All coupling capacitors should be selected so that they will not cause any significant attenuation at low frequencies, taking input resistances into account. The TX pin is internally biased at 1.5V. Please contact Silicon Labs for additional assistance with interfacing the IA3223. IA3222/IA3223 28 ...
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... Rx - Figure 27: Single-ended interface 2k Tx Rx+ + Rx- - Figure 28: Differential interface — without reference Tx+ + Tx- - ACRef Rx+ + Rx- - 100nF Figure 29: Differential interface — with reference IA3222/IA3223 - To PWM converter + Transmitter HPF - 0.6V reference + From PWM converter Receiver LPF ACRef IA3223 ACRef IA3223 Rx 29 ...
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... All of these signals can be read from IA3223 registers. Depending on the setting of the LSR bit, either the ring-detection signal or the LACT signal can be output to the LineStat (line status) pin. ...
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... The IA3223 has a true line-polarity detector. Line polarity is directly sensed in the IA3222 Line-Side chip and this information is sent across the isolation barrier to the IA3223 System-Side chip. Line polarity reversal may take ms. Through this transition all three detectors Line In Use, Line Activity, and Ring may be triggered. A line reversal can be qualified by determining if the change in polarity is stable for 50 to 100 ms ...
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... Expected ring cadence both at LineStat pin and at RNG bit LP bit changed compared to before interrupt, stable for 100 ms LIU bit high if previously low, stable for 100 ms LIU bit low if previously high, stable for 100 ms No ring cadence or change LIU bits IA3222/IA3223 ® series 32 ...
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... Drops over 500 ms indicate disconnect while shorter drops indicate call waiting. Consequently important to time the duration of line drops with at least 10 ms resolution. Line drop is detected by the IA3223 System Side and flagged as the LD (Line Drop) status bit when the IA3222 Line Side receives insufficient loop current to keep it operational (less than 10 mA) ...
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... Enable the current sensor. The loop current can now be read as incoming-data DC offset from the DC reference voltage. The sensitivity of the current sensor is approximately 1. offset for every loop current. Note that both the DC-offset correction factor and the gain change with the Line-Side termination impedance setting. IA3222/IA3223 34 ...
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... In other words, the power lines and the telephone cable form a very low impedance pulse transformer that may couple to the telephone line the IA3222/IA3223 RMS 35 ...
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... If part of the arc gap is on the circuit board it is important that the ends not have insulating silkscreen over them. For most worldwide applications, the gap should be at least 2.5 mm. This means that the other creepage (surface distance) distances should be at least 3 mm. IA3222/IA3223 . Even though longitudinal transients RMS ...
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... Line cross is a much rarer event than lightning surges. Over the life of the product, this typically has less than a 1% chance of happening. A line cross can occur from the user side or from the telephone system side. If the chassis of a telephone product somehow gets shorted to one side of the AC power line, then the DAA isolation protects telephone-company technicians and equipment from IA3222/IA3223 37 ...
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... The reason is that opto-isolated systems need a gain of almost 100 on the transfer and servo photodiodes because of the typical 1 % current-transfer ratio. Normally, there is a small amount of isolation capacitance in the sensitive servo or transfer photodiode to the effect that at 3 kHz the common-mode balance may be 80dB or less. IA3222/IA3223 to AC ...
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... EN 55024 or even to Brazil’s more demanding Anexo a Resolução No 237, a pair of 470 pF high-voltage capacitors between Tip/Ring and the chassis ground is normally sufficient. In general, filtering components work both ways: any RF solution that works well for radiated signals will work well for susceptibility in the same frequency range. IA3222/IA3223 39 ...
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... Both of these are very critical for high-speed modems. A hidden critical element for high-speed modems is hybrid thermal drift. If the hybrid return loss, transmitter or receiver gain drifts by even a small amount (less than -60 dB) between initial training and several minutes later, the modem performance can be greatly degraded since the un- IA3222/IA3223 40 ...
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... In some digital DAAs, the sampling delay prevents this except for very low frequencies. But since the IA3222/3223 uses eight-times oversampling, line to Rx pin and Tx pin to line delays are significantly less, thus making impedance synthesis possible. IA3222/IA3223 41 ...
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... PACKAGE INFORMATION QSOP-16 and QSOP-20 Packages MSOP-10 Package SOIC-8 Package (JEDEC Outline MS-012AA) IA3222/IA3223 42 ...
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... DESCRIPTION IA3222A – Line Side US/Japan DAA IC IA3222B – Line Side Enhanced Worldwide DAA IC IA3223 – System Side Worldwide DAA IC IA3223A – System Side Worldwide DAA IC with pin hook control Silicon Labs, Inc. 400 West Cesar Chavez Austin, Texas 78701 Tel: 512.416.8500 Fax: 512 ...