SI3230-KT Silicon Laboratories Inc, SI3230-KT Datasheet
SI3230-KT
Specifications of SI3230-KT
Related parts for SI3230-KT
SI3230-KT Summary of contents
Page 1
... CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3230M only supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry. ...
Page 2
... Si3230 2 Preliminary Rev. 0.96 ...
Page 3
... DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 5. Pin Descriptions: Si3230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7. Ordering Guide1 103 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Document Change List ...
Page 4
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability Operation above 125 C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3230 DDD DDA1 DDA2 I IN ...
Page 5
... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3230 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
Page 6
... Si3230 Table 3. AC Characteristics (Continued 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Longitudinal to Metallic Balance Metallic to Longitudinal Balance Longitudinal Impedance Longitudinal Current per Pin Notes: 1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. ...
Page 7
... TIP to ground I = 11.43 mA THR I = 40.64 mA THR User Programmable Register 70 and Indirect Register 36 5 REN load; sine wave 160 Ω –75 V LOOP BAT Programmable in Indirect OS Register 19 Preliminary Rev. 0.96 Si3230 Min Typ Max 0 — 160 –10 — 10 –4 — 4 — 160 — –4 — ...
Page 8
... DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity INLE (6-bit resolution) Gain Error (voltage) Gain Error (current) Table 6. Si3230 DC Characteristics 4. 5. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol High Level Input Voltage V IH ...
Page 9
... Table 7. Si3230 DC Characteristics 3. 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol High Level Input Voltage V IH Low Level Input Voltage V IL High Level Output Voltage V OH Low Level Output Voltage V OL Input Leakage Current I L Table 8. Power Supply Characteristics ...
Page 10
... Si3230 Table 8. Power Supply Characteristics (Continued 3. 5. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol 3 V Supply Current BAT Notes 3.3 V. DDD DDA 5.25 V. DDD DDA current from V (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, ...
Page 11
... Figure 2. SPI Timing Diagram Preliminary Rev. 0.96 Si3230 = Min Typ Max Unit µsec 0.062 — — — — 25 — — 25 — — 20 — — 20 — — — — 20 — — 25 — — 20 — — 440 — — ...
Page 12
... Only one component per system R21 needed All circuit ground should have a single- point connection to the ground plane . Figure 3. Si3230/Si3230M Application Circuit Using Si3201 Table 11. Si3230/Si3230M + Si3201 External Component Values Component (s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, ±20% C3,C4 C5,C6 C15,C16,C17,C24 ...
Page 13
... Values and configurations for these components can be derived from Table 17 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 4. Si3230 DC-DC Converter Circuit Table 12. Si3230 DC-DC Converter Component Values Component ( µF, 100 V, Electrolytic, ±20% C10 0.1 µ ...
Page 14
... Si3230 SDCH SDCL DCFF DCDRV Figure 5. Si3230M MOSFET/Transformer DC-DC Converter Circuit Table 13. Si3230M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* C25* C27 470 pF, 100 V, X7R, ±20% R17 R18 1/4 W, ±5% (See AN45 or Table 21 for value selection) R19,R20 1/10 W, ± ...
Page 15
... App Note 45. 2. Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane. Figure 6. Si3230/Si3230M Typical Application Circuit Using Discrete Components Table 14. Si3230/Si3230M External Component Values—Discrete Solution Component 10 µ Ceramic Low Leakage Electrolytic, ±20% C1,C2 220 nF, 100 V, X7R, ± ...
Page 16
... Si3230 VINp TX gain = 0.6622 CMlevel VINm VOUTm VOUTp RX gain = 1.2346 Figure 7. Interface to Broadcom BCM11xx Table 15. External Component Values—BCM11xx Interface Component C1 0.1 µ Y5V, ±20% C5, C6 0.1 µF, 100 V, X7R, ±20% 121 Ω, 1/10 W, ±1% R1, R2 R5, R8 kΩ, 1/10 W, ±1% R6 kΩ ...
Page 17
... Table 16. Component Value Selection for Si3230 Component R28 1/ resistor For V DD For V DD R29 1/ resistor For V CLAMP For V CLAMP For V CLAMP Table 17. Component Value Selection Examples for DC-DC Converter VDC Maximum Ringing Load/Loop Resistance 3 REN/117 Ω REN/117 Ω REN/117 Ω Note: There are other system and software conditions that influence component value selection. Please refer to “AN45: “ ...
Page 18
... SLIC, DTMF detection, and signal generation functions needed for a complete analog telephone interface when connected to an external codec. The ProSLIC performs all battery, overvoltage, ringing, supervision, and test functions. Unlike most monolithic SLICs, the Si3230 does not require externally supplied high-voltage supplies ...
Page 19
... TIP tri-stated, RING active; used for ground start. Ringing waveform applied to TIP and RING. V > RING TIP V > audio signal paths powered on. RING TIP RING tri-stated, TIP active. Preliminary Rev. 0.96 Si3230 state drives programmable ringing – reported as a TIP RING – –I )/2, is reported ...
Page 20
... Si3230 Table 21. Measured Realtime Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – TIP V ) RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense ...
Page 21
... Bits corre- n/a spond Q6, respectively Bits corre- n/a spond Q6, respectively 0 = manual mode n enter open state upon power alarm Preliminary Rev. 0.96 Si3230 Register Location* Bits PWRMP[2:0] Direct Register 76 PWROM[7:0] Direct Register 77 PPT12[7:0] Indirect Register 32 PPT34[7:0] Indirect Register 33 PPT56[7:0] Indirect Register 34 ...
Page 22
... Si3230 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or on- hook active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter ...
Page 23
... It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3230 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (t ) the calibration can be initiated. ...
Page 24
... These inputs should be calibrated by writing the DCCAL bit (bit 7) of the dc-dc Converter Switching Delay register, direct Register 93, after the dc-dc converter has been turned on. Because the Si3230 dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage (V BAT ...
Page 25
... TIP RING BAT Range Resolution n/a n/a n/a n 15.564 us 61.035 1.892 us) + 61.035 –94 –94 – 1 –13.5 V Preliminary Rev. 0.96 Si3230 Constant V Region R LOOP V TIP RING BAT Register Bit Location DCOF Direct Register 14 DCCAL Direct Register 93 DCN[7:0] Direct Register 92 DCTOF[4:0] ...
Page 26
... Si3230 2.2.5. DC-DC Converter Enhancements There are two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop ...
Page 27
... REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1). 0.49819 0.5 = 2370 = 942h Preliminary Rev. 0.96 Si3230 phase frequency-shift keying (FSK) 27 ...
Page 28
... Si3230 Table 25. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer ...
Page 29
... Disabled Enabled/ ROE Disabled seconds RAT[15: seconds RIT[15:0] Ringing State = 100b LF[2: –94.5 V VBATH[5: 94.5 V ROFF[15:0] Preliminary Rev. 0.96 Si3230 circuit with programmable the ringing waveform is Location Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Registers 48 and 49 Direct Registers 50 and 51 ...
Page 30
... Si3230 Table 26. Registers for Ringing Generation (Continued) Ringing frequency Ringing amplitude Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
Page 31
... Figure 14. The primary input to the system is the Loop Current Sense value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the Preliminary Rev. 0.96 Si3230 V N AC,PK REN × ...
Page 32
... Si3230 ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter is compared to a programmable threshold, RPTP (indirect Register 29). ...
Page 33
... Description / Range Register Bits Sets oscillator frequency Sets oscillator amplitude 0 to PLSX (full amplitude seconds seconds Status and control registers PSTAT, PMAE, Preliminary Rev. 0.96 Si3230 RTDI hex decimal hex Desired V – ...
Page 34
... Si3230 The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The volume value is incremented by the value in the PLSD register (indirect Register 23 kHz rate. The sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0 to 7FFF in increments of PLSD so the value of PLSD will set the slope of the ramp ...
Page 35
... Preliminary Rev. 0.96 Si3230 35 ...
Page 36
... The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected (XAC) and a Power alarm DTMF digit detected (Si3230 and Si3211 only) Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired is m Ringing inactive timer expired ) ...
Page 37
... LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. Don't Care High Impedance Figure 17. Serial Write 8-Bit Mode Preliminary Rev. 0.96 Si3230 beginning ...
Page 38
... Si3230 SCLK CS SDI SDO High Impedance 38 Don't Care Figure 18. Serial Read 8-Bit Mode Preliminary Rev. 0.96 Don't Care ...
Page 39
... Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. CS SDO CS SDO CS SDO CS SDO Address Byte R/W Figure 19. SPI Daisy Chain Mode Preliminary Rev. 0.96 Si3230 SDI0 SDI SDITHRU SDI1 SDI SDITHRU SDI2 SDI SDITHRU SDI3 SDI SDITHRU Data Byte ...
Page 40
... Si3230 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 9 Audio Gain Control 10 Two-Wire Impedance Synthesis Control 11 Hybrid Control 14 Power Down Control 1 15 Power Down Control 2 18 Interrupt Status 1 19 Interrupt Status 2 ...
Page 41
... External Bipolar Transistor Control Bit 7 Bit 6 Bit 5 Bit 4 OAT1[15:8] OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] PAT[7:0] PAT[15:8] PIT[7:0] PIT[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE Preliminary Rev. 0.96 Si3230 Bit 3 Bit 2 Bit 1 Bit 0 FSKDAT LF[2:0] ETBO[1:0] ETBA[1:0] 41 ...
Page 42
... Si3230 Table 30. Direct Register Summary (Continued) Register Name 66 Battery Feed Control 67 Automatic/Manual Control 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High Battery Voltage 75 Low Battery Voltage ...
Page 43
... Calibration Result 108 Enhancement Enable Bit 7 Bit 6 Bit 5 Bit 4 DCPW[7:0] CAL CALSP CALR CALM1 CALMG1[3:0] DACOF[7:0] ILIMEN FSKEN DCEN ZSEXT Preliminary Rev. 0.96 Si3230 Bit 3 Bit 2 Bit 1 Bit 0 CALT CALD CALC CALIL CALM2 CALDAC CALADC CALCM CALGMR[R4:0] CALGMT[4:0] CALGD[4:0] CALGC[4:0] CALGIL[3:0] ...
Page 44
... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3230 01 = Reserved 10 = Reserved 11 = Reserved 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. 44 ...
Page 45
... Receive signal muted. 3:2 ATX[1:0] Analog Transmit Path Gain –3 3 ATX gain = 0 dB; analog transmit path muted. 1:0 ARX[1:0] Analog Receive Path Gain –3 3 Analog receive path muted TXM RXM ATX[1:0] R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 ARX[1:0] R/W 45 ...
Page 46
... Si3230 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off Reserved 3 TISE Two-Wire Impedance Synthesis Enable Two-wire impedance synthesis disabled Two-wire impedance synthesis enabled. ...
Page 47
... Off 3 Reserved Read returns zero. 2:0 HYBA[2:0] Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.94 dB 110 = –2.77 dB 111 = Off R/W Function Preliminary Rev. 0.96 Si3230 HYBA[2:0] R/W 47 ...
Page 48
... Pulse Metering DAC Power-On Control Automatic power control Override automatic control and force pulse metering DAC circuitry on. 4 DCOF DC-DC Converter Power-Off Control (Si3230 only Automatic power control Override automatic control and force dc-dc circuitry off. Si3211/Si3212 = Read returns 1; it cannot be written. 3 MOF Monitor ADC Power-Off Control ...
Page 49
... Manual power control; GMON controls on/off state. 0 GMON Transconductance Amplifier On/Off Power Control. When GMM = Analog to digital converter powered off Analog to digital converter powered on. GMON has no effect when GMM = ADCON DACM DACON R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 GMM GMON R/W R/W R/W 49 ...
Page 50
... Si3230 Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP RGIP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 6 PMAP Pulse Metering Active Timer Interrupt Pending. ...
Page 51
... Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 RTIP Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending Q3AP Q2AP Q1AP R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 LCIP RTIP R/W R/W R/W 51 ...
Page 52
... This bit is set once a pending indirect register service request has been completed. Writ- ing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 DTMFP DTMF Tone Detected Interrupt (Si3230 and Si3211 only). Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. Si3212 = Reserved; read returns 0. 52 ...
Page 53
... Oscillator 2 Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 1 O1IE Oscillator 1 Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 0 O1AE Oscillator 1 Active Timer Interrupt Enable Interrupt masked Interrupt enabled RGAE O2IE O2AE R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 O1IE O1AE R/W R/W R/W 53 ...
Page 54
... Si3230 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm Q5 Interrupt Enable Interrupt masked Interrupt enabled. 5 Q4AE Power Alarm Q4 Interrupt Enable. ...
Page 55
... Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 DTMFE DTMF Tone Detected Interrupt Enable Interrupt masked Interrupt enabled CMCE R/W Function Preliminary Rev. 0.96 Si3230 INDE DTMFE R/W R/W 55 ...
Page 56
... Si3230 Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 DIG[3:0] DTMF Digit. 0001 = “1” 0010 = “2” ...
Page 57
... IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation IDA[7:0] R/W Function IDA[15:8] R/W Function Preliminary Rev. 0.96 Si3230 ...
Page 58
... Si3230 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate— ...
Page 59
... Oscillator 1 Enable Disable oscillator Enable oscillator. 1:0 O1SO[1:0] Oscillator 1 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths OZ1 O1TAE O1TIE R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 O1E O1SO[1:0] R/W R/W 59 ...
Page 60
... Si3230 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 OZ2 Oscillator 2 Zero Cross Enable Signal terminates after active timer expires Signal terminates at zero crossing. ...
Page 61
... Ringing Oscillator Enable Ringing oscillator disabled Ringing oscillator enabled. 1 RVO Ringing Voltage Offset offset added to ringing signal offset added to ringing signal. 0 TSWS Trapezoid/Sinusoid Waveshape Select Sinusoid 1 = Trapezoid RTAE RTIE ROE R R/W R/W Function Preliminary Rev. 0.96 Si3230 RVO TSWS R R/W R/W 61 ...
Page 62
... Si3230 Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns zero. 4 PMAE Pulse Metering Active Timer Enable Disable timer Enable timer. ...
Page 63
... OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[7:0] Oscillator 1 Inactive Timer. LSB = 125 µ OAT1[7:0] R/W Function OAT1[15:8] R/W Function OIT1[7:0] R/W Function Preliminary Rev. 0.96 Si3230 ...
Page 64
... Si3230 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. ...
Page 65
... Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PAT[7:0] Pulse Metering Active Timer. LSB = 125 µ OIT2[7:0] R/W Function OIT2[15:8] R/W Function PAT[7:0] R/W Function Preliminary Rev. 0.96 Si3230 ...
Page 66
... Si3230 Register 45. Pulse Metering Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PAT[15:8] Pulse Metering Active Timer. Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name ...
Page 67
... RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[7:0] Ringing Inactive Timer. LSB = 125 µ RAT[7:0] R/W Function RAT[15:8] R/W Function RIT[7:0] R/W Function Preliminary Rev. 0.96 Si3230 ...
Page 68
... Si3230 Register 51. Ringing Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Ringing Inactive Timer. Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. ...
Page 69
... LF[2:0] Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function Preliminary Rev. 0.96 Si3230 LF[2:0] R/W 69 ...
Page 70
... Si3230 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 CBY Capacitor Bypass Capacitors CP (C1) and CM (C2) in circuit Capacitors CP (C1) and CM (C2) bypassed. ...
Page 71
... Normal operation tracks VBATH register. BAT 2:1 Reserved Read returns zero. 0 TRACK DC-DC Converter Tracking Mode will not decrease below VBATL. BAT tracks V BAT VOV FVBAT R/W R/W Function OV . RING Preliminary Rev. 0.96 Si3230 TRACK R/W , which is defined in indirect Register 41. 71 ...
Page 72
... Si3230 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. 5 MNDIF Differential Mode Manual/Automatic Select. ...
Page 73
... LCDI[6:0] Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms DBIRAW Function LCDI[6:0] R/W Function Preliminary Rev. 0.96 Si3230 RTP LCR ...
Page 74
... Si3230 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12 ...
Page 75
... VOC[5:0] R/W Function is positive RING is negative RING VCM[5:0] R/W Function for forward active and forward on-hook trans- TIP for reverse active and reverse on-hook transmission states. RING Preliminary Rev. 0.96 Si3230 –V ). TIP RING –V ). Value may TIP RING ...
Page 76
... Si3230 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = – ...
Page 77
... Line Power Output Monitor. This register reports the realtime power output of the transistor selected using PWRMP. The range (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4 Function PWROM[7:0] R Function Preliminary Rev. 0.96 Si3230 PWRMP[2:0] R ...
Page 78
... Si3230 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ( Positive loop voltage ( Negative loop voltage (V 5:0 LVS[5:0] Loop Voltage Sense Magnitude ...
Page 79
... Reset settings = 0000_0000 Bit Name 7:0 VBATS1[7:0] Battery Voltage Sense 1. This register is one of two registers that reports the realtime voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps VTIP[7:0] R Function VRING[7:0] R Function VBATS1[7:0] R Function Preliminary Rev. 0.96 Si3230 with respect BAT 79 ...
Page 80
... Si3230 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps. Register 84. Transistor 1 Current Sense ...
Page 81
... Register 88. Transistor 5 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ5[7:0] Transistor 5 Current Sense. This register reports the realtime current through Q5. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps IQ3[7:0] R Function IQ4[7:0] R Function IQ5[7:0] R Function Preliminary Rev. 0.96 Si3230 ...
Page 82
... Si3230 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the realtime current through Q6. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps. Register 92. DC-DC Converter PWM Period Bit D7 D6 Name ...
Page 83
... DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3230 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3230 DCFF pin polarity is same as DCDRV pin (Si3230M). ...
Page 84
... Si3230 Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width. Pulse width of DCDRV is given (DCPW – DCTOF – 4) 61.035 ns DCPW[7:0] R Function Preliminary Rev. 0. ...
Page 85
... Common Mode DAC Gain Calibration Normal operation or calibration complete Calibration enabled or in progress. 0 CALIL I Calibration. LIM 0 = Normal operation or calibration complete Calibration enabled or in progress CALR CALT CALD R/W R/W R/W Function Preliminary Rev. 0.96 Si3230 CALC CALIL R/W R/W R/W settling at the beginning of the BAT 85 ...
Page 86
... Si3230 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. 3 CALM2 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. ...
Page 87
... Register 100. Differential Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGD[4:0] Differential DAC Gain Calibration Result CALGMR[4:0] R/W Function CALGMT[4:0] R/W Function CALGD[4:0] R/W Function Preliminary Rev. 0.96 Si3230 ...
Page 88
... Si3230 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result Bit D7 D6 Name ...
Page 89
... Register 106. Common Mode Calibration Result Bit D7 D6 Name Type Reset settings = 0010_0000 Bit Name 7:6 Reserved Read returns zero. 5:0 CMBAL[5:0] Common Mode Calibration Result DACP DACN R/W R/W Function DACOF[7:0] R/W Function CMBAL[5:0] Function Preliminary Rev. 0.96 Si3230 ADCP ADCN R/W R ...
Page 90
... Si3230 Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result. Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W ...
Page 91
... When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively Loop closure hysteresis disabled Loop closure hysteresis enabled. Function to V external battery supplies (EXTBAT = 1). BATH BATL Preliminary Rev. 0.96 Si3230 91 ...
Page 92
... Si3230 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. ...
Page 93
... DTMF Power Minimum Threshold. This register sets the threshold for the minimum total power in the DTMF calculation, under which the calculation is ignored. 12 DTMF Hot Limit Threshold. This register sets the two-step AGC in the DTMF path. Description Preliminary Rev. 0.96 Si3230 Reference Page ...
Page 94
... Si3230 4.2. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes ...
Page 95
... This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –∞ dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Description D11 D10 DACG[11:0] ADCG[11:0] Description Preliminary Rev. 0.96 Si3230 Reference Page ...
Page 96
... VMIND[3:0 LCRTL[5:0] *Note: Si3230 only. Table 38. SLIC Control Indirect Registers Description Addr. 28 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hys- teresis is enabled (direct Register 108, bit 0). The range is 0– 1.27 mA steps. See "2.1.6. Loop Closure Detection" on page 22. ...
Page 97
... FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). Table 39. FSK Control Indirect Registers Summary Addr. D15 D14 D13 D12 99 100 101 102 103 104 Description Voltage (Si3230 only supplied by the dc-dc converter. OV should be set between 0 and should be set between 0 and 13 D11 D10 ...
Page 98
... Si3230 Table 40. FSK Control Indirect Registers Description Addr. 99 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. ...
Page 99
... Pin Descriptions: Si3230 FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC Pin # Pin # Name QFN TSSOP Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high imped- ance. When active, the serial port is operational. ...
Page 100
... Si3230 Pin # Pin # Name QFN TSSOP 5 9 SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the con- verter VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry IREF Current Reference. Connects to an external resistor used to provide a high accuracy reference current ...
Page 101
... Serial Port Data Out. Serial port control data output SDI Serial Port Data In. Serial port control data input SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description Preliminary Rev. 0.96 Si3230 101 ...
Page 102
... Si3230 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 102 TIP 1 16 ITIPP ITIPN RING ...
Page 103
... Ordering Guide Device Description Si3230-X-FM ProSLIC Si3230-X-GM ProSLIC Si3230M-X-FM ProSLIC Si3230M-X-GM ProSLIC Si3230-KT ProSLIC Si3230-GT ProSLIC Si3230M-KT ProSLIC Si3230M-GT ProSLIC Si3201-FS Line Interface Si3201-GS Line Interface Si3201-KS Line Interface Si3201-BS Line Interface Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel options; 2500 quantity per reel. ...
Page 104
... Si3230 8. Package Outline: 38-Pin QFN Figure 20 illustrates the package details for the Si3230. Table 41 lists the values for the dimensions shown in the illustration. Figure 20. 38-Pin Quad Flat No-Lead Package (QFN) Table 41. Package Diagram Dimensions Symbol aaa bbb ccc ddd Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. ...
Page 105
... Package Outline: 38-Pin TSSOP Figure 21 illustrates the package details for the Si3230. Table 42 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C Figure 21. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 42. Package Diagram Dimensions ccc 38x ...
Page 106
... Si3230 10. Package Outline: 16-Pin SOIC Figure 22 illustrates the package details for the Si3201. Table 43 lists the values for the dimensions shown in the illustration . –A– Seating Plane Figure 22. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 43. Package Diagram Dimensions 106 . –B– ...
Page 107
... Updated Figure 3 on page 12. C18, C19 changed from 1.0 µF to 4.7 µF. Updated Figure 4 on page 13. C10 changed from 0.1 µF. Updated "5. Pin Descriptions: Si3230" on page 99. Added QFN pin description. Updated "7. Ordering Guide1,2" on page 103. Added "8. Package Outline: 38-Pin QFN" on page 104. Updated " ...
Page 108
... Si3230 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...