SI3225-KQ Silicon Laboratories Inc, SI3225-KQ Datasheet - Page 69

• Manufacturer Part Number: SI3225-KQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3225-KQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: SLIC
• Supply Voltage (min): 3.13 V
• Supply Current: 22 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PCM Interface
The
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select,
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power of 2 increments. (768 kHz,
1.536 MHz
Timeslots for data transmission and reception are
independently
PCMTXLO, PCMRXHI, and PCMRXLO. Setting the
correct starting point of the data configures the part to
support long FSYNC and short FSYNC variants, IDL2 8-
bit, 10-bit, B1 and B2 channel time slots. DTX data is
high-impedance except for the duration of the 8-bit PCM
Dual
PCM
and
ProSLIC
PCLK_CNT
PCLK_CNT
Transmit
configured
FSYNC
FSYNC
PCLK
1.544 MHz
DRX
DTX
PCLK
DRX
DTX
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
HI-Z
devices
HI-Z
Start
0
0
with
MSB
MSB
also
1
1
contain
Count
MSB
MSB
2
2
the
are
3
3
(PCMTXHI/
a
PCMTXHI,
4
available.)
4
Preliminary Rev. 0.91
flexible
5
5
6
6
7
7
transmit. DTX returns to high-impedance on the
negative edge of PCLK during the LSB or on the
positive edge of PCLK following the LSB. This is based
on the setting of the PCMTRI bit of the PCM Mode
Select register. Tristating on the negative edge allows
the transmission of data by multiple sources in adjacent
timeslots without the risk of driver contention. In addition
to 8-bit data modes, there is a 16-bit mode provided for
testing. This mode can be activated via the PCMF bits
of the PCM Mode Select register. Setting the PCMTXHI/
PCMTXLO or PCMRXHI/PCMRXLO register greater
than the number of PCLK cycles in a sample period
stops data transmission because PCMTXHI/PCMTXLO
or PCMRXHI/PCMRXLO do not equal the PCLK count.
Figures 51–53 illustrate the usage of the PCM highway
interface to adapt to common PCM standards.
LSB
LSB
8
8
LSB
LSB
9
9
10
10
11
11
12
12
HI-Z
HI-Z
13
13
14
14
Si3220/Si3225
15
15
16
16
17
17
18
18
69