DS2155G+T&R Maxim Integrated Products, DS2155G+T&R Datasheet - Page 172

• Manufacturer Part Number: DS2155G+T&R
• Description: IC TXRX T1/E1/J1 1 CHIP 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS2155G+T&R

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

26.3 BERT Register Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes
to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into
registers BBC1/BBC2/BBC3/BBC4 and BEC1/BEC2/BEC3 and clears the internal count. This bit should be
toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set
again for subsequent loads.
Bits 2 to 4/Pattern Select Bits (PS0 to PS2)
PS2 PS1
Bit 5/Receive Invert-Data Enable (RINV)
Bit 6/Transmit Invert-Data Enable (TINV)
Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to
be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be
cleared and set again for subsequent loads.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 = do not invert the incoming data stream
1 = invert the incoming data stream
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
PS0
TC
7
0
0
1
0
1
0
1
0
1
Pseudorandom 2E7 - 1
Pseudorandom 2E11 - 1
Pseudorandom 2E15 - 1
Pseudorandom pattern QRSS. A 2
restrictions.
Repetitive pattern
Alternating word pattern
Modified 55 octet (Daly) pattern. The Daly pattern is a repeating 55 octet
pattern that is byte-aligned into the active DS0 time slots. The pattern is
defined in an ATIS (Alliance for Telecommunications Industry Solutions)
Committee T1 Technical Report Number 25 (November 1993).
Pseudorandom 2E9 - 1
TINV
BC1
BERT Control Register 1
E0h
6
0
RINV
5
0
PS2
4
0
Pattern Definition
172 of 238
20
- 1 pattern with 14 consecutive zero
PS1
3
0
PS0
2
0
LC
1
0
RESYNC
0
0