DS21Q50L+ Maxim Integrated Products, DS21Q50L+ Datasheet
DS21Q50L+
Specifications of DS21Q50L+
Related parts for DS21Q50L+
DS21Q50L+ Summary of contents
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GENERAL DESCRIPTION The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 ...
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INTRODUCTION ...............................................................................................................................6 2. PIN DESCRIPTION............................................................................................................................9 2 UNCTION ESCRIPTION 2.1.1 System (Backplane) Interface Pins .......................................................................................................15 2.1.2 Alternate Jitter Attenuator ....................................................................................................................16 2.1.3 Clock Synthesizer..................................................................................................................................16 2.1.4 Parallel Port Control Pins....................................................................................................................16 2.1.5 Serial Port Control Pins .......................................................................................................................17 2.1.6 Line ...
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CMI (CODE MARK INVERSION).................................................................................................64 18. INTERLEAVED PCM BUS OPERATION....................................................................................66 19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68 19 ECEIVE IMING IAGRAMS 19 RANSMIT IMING 20. OPERATING PARAMETERS ........................................................................................................74 21. AC TIMING PARAMETERS AND DIAGRAMS .........................................................................75 21.1 M ...
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Figure 1-1. Block Diagram ............................................................................................................................8 Figure 3-1. Serial Port Operation Mode 1 ...................................................................................................21 Figure 3-2. Serial Port Operation Mode 2 ...................................................................................................21 Figure 3-3. Serial Port Operation Mode 3 ...................................................................................................22 Figure 3-4. Serial Port Operation Mode 4 ...................................................................................................22 Figure 16-1. Typical ...
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Table 2-1. Pin Assignments (by Function) ....................................................................................................9 Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12 Table 3-1. Bus Mode Select.........................................................................................................................20 Table 3-2. Register Map ..............................................................................................................................23 Table 4-1. Sync/Resync Criteria..................................................................................................................26 Table 5-1. Alarm Criteria ............................................................................................................................34 Table 8-1. Transmit PRBS Mode Select......................................................................................................45 ...
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INTRODUCTION The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The IBO allows up to eight E1 ...
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Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125µs frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots ...
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Figure 1-1. Block Diagram MCL VCO/PLL RECEIVE SIDE RRING1 RTIP1 TRANSMIT SIDE TRING1 TTIP1 TRANSCEIVER 1of 4 Parallel & Test Control Port (routed to all blocks) User Outputs Select Elastic Store DATA And CLOCK IBO Buffer SYNC Receive-Side Framer Sync ...
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PIN DESCRIPTION Table 2-1. Pin Assignments (by Function) PIN PARALLEL PORT ENABLED 71 4/8/16MCK AJACKI 69 AJACKO 50 ALE(AS)/A5 96 BTS0 97 BTS1 D0/AD0 20 ...
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NAME PIN PARALLEL PORT ENABLED 60 OUTB1 35 OUTB2 10 OUTB3 85 OUTB4 95 PBTS RD (DS REFCLK 67 RRING1 42 RRING2 17 RRING3 92 RRING4 63 RSER1 38 RSER2 13 RSER3 88 RSER4 64 RSYNC1 39 RSYNC2 ...
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PIN PARALLEL PORT ENABLED 56 TSER2 31 TSER3 6 TSER4 82 TSYNC1 57 TSYNC2 32 TSYNC3 7 TSYNC4 76 TTIP1 51 TTIP2 26 TTIP3 1 TTIP4 78 TVDD1 53 TVDD2 28 TVDD3 3 TVDD4 77 TVSS1 52 TVSS2 27 TVSS3 ...
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Table 2-2. Pin Assignment (by LQFP Pin Number) NAME PIN PARALLEL PORT ENABLED 1 TTIP4 2 TVSS4 3 TVDD4 4 TRING4 5 TCLK4 6 TSER4 7 TSYNC4 8 DVSS4 9 DVDD4 10 OUTB3 11 OUTA3 12 SYSCLK3 13 RSER3 14 ...
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NAME PIN PARALLEL PORT ENABLED ALE (AS)/A5 51 TTIP2 52 TVSS2 53 TVDD2 54 TRING2 55 TCLK2 56 TSER2 57 TSYNC2 58 DVSS2 59 DVDD2 60 OUTB1 61 OUTA1 ...
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NAME PIN PARALLEL PORT ENABLED 87 SYSCLK4 88 RSER4 89 RSYNC4 90 RVSS1 91 RTIP4 92 RRING4 93 RVDD1 94 INT 95 PBTS 96 BTS0 97 BTS1 TS0 100 TS1 — EQVSS1 — EQVSS2 — EQVSS3 — ...
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Pin Function Description 2.1.1 System (Backplane) Interface Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal ...
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Alternate Jitter Attenuator Signal Name: AJACKI Signal Description: Alternate Jitter Attenuator Clock Input Signal Type: Input Clock input to alternate jitter attenuator. Signal Name: AJACKO Signal Description: Alternate Jitter Attenuator Clock Output Signal Type: Output Clock output of alternate ...
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Signal Name: PBTS Signal Description: Parallel Bus Type Select Signal Type: Input Used to select between Motorola and Intel parallel bus types. Signal Name: AD0 to AD7/SDO Signal Description: Data Bus or Address/Data Bus [D0 to D6] Data Bus or ...
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Signal Name: ICES Signal Description: Input Clock Edge Select Signal Type: Input Used to select which SCLK clock edge samples data at SDI. Signal Name: OCES Signal Description: Output Clock Edge Select Signal Type: Input Used to select which SCLK ...
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Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and ...
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HOST INTERFACE PORT The DS21Q50 is controlled either through a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Motorola ...
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Figure 3-1. Serial Port Operation Mode 1 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK) SCLK SDI R/W (lsb) ...
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Figure 3-3. Serial Port Operation Mode 3 ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK) SCLK SDI R/W (lsb) ...
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Register Map Table 3-2. Register Map ADDRESS R R R/W 0B R/W 0C — 0D — 0E — 0F ...
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ADDRESS R/W 2C R/W 2D R/W 2E R/W 2F R/W TEST1 (set to 00h) Note 1: The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0). Note 2: Only the ...
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Power-Up Sequence On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of the internal ...
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Table 4-1. Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frame N and FAS and FAS not present in frame Two valid MF alignment CRC4 words found within 8ms Valid MF ...
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Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 12 Hex Bit 7 6 Name FLB THDB3 NAME BIT Framer Loopback. See Section FLB loopback disabled 1 = loopback enabled Transmit HDB3 Enable THDB3 6 ...
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Framer Loopback When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter back to the receiver. When FLB ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are ...
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Remote Loopback When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues to ...
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Register Name: CCR5 Register Description: Common Control Register 5 Register Address: 16 Hex Bit 7 6 Name LIUODO CDIG NAME BIT Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs are open drain or not. ...
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STATUS AND INFORMATION REGISTERS A set of four registers—status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register (SSR)—contains information about the DS21Q50 framer’s real-time status When a particular event has occurred (or ...
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Register Name: RIR Register Description: Receive Information Register Register Address: 08 Hex Bit 7 6 Name RGM1 RGM0 NAME BIT RGM1 7 Receive Gain Monitor Bit 1. See the Level Indication table below for level indication. RGM0 6 Receive Gain ...
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Register Name: SSR Register Description: Synchronizer Status Register Register Address: 09 Hex Bit 7 6 Name CSC5 CSC4 NAME BIT CSC5 7 CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CSC4 6 CRC4 Sync Counter Bit 4 CSC3 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 0A Hex Bit 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones. Set when the contents of time slot 16 contain fewer than three RSA1 7 0s over ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 18 Hex Bit 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones RSA1 interrupt masked 1 = interrupt enabled Receive Distant MF Alarm RDMA ...
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Register Name: SR2 Register Description: Status Register 2 Register Address: 0B Hex Bit 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) RMF 7 on receive multiframe boundaries. ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19 Hex Bit 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe RMF interrupt masked 1 = interrupt enabled Receive Align Frame RAF 6 0 ...
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ERROR COUNT REGISTERS A set of four counters in each transceiver of the DS21Q50 record bipolar (BPV) or code violations (CV), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in ...
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CRC4 Error Counter CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 ...
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FAS Error Counter FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the frame alignment signal (FAS) in time slot 0. This ...
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DS0 MONITORING FUNCTION Each DS21Q50 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to ...
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Register Name: TDS0M Register Description: Transmit Ds0 Monitor Register Register Address: 22 Hex Bit 7 6 Name B1 B2 NAME BIT Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit transmitted ...
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Register Name: RDS0M Register Description: Receive Ds0 Monitor Register Register Address: 2A Hex Bit 7 6 Name B1 B2 NAME BIT B1 7 Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received Receive DS0 ...
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PRBS GENERATION AND DETECTION The DS21Q50 can transmit and receive the 2 T O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0 any single ...
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SYSTEM CLOCK INTERFACE A single system clock interface (SCI) is common to the four DS21Q50 transceivers. The SCI allows any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s are ...
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Table 9-1. Master Port Selection SCS2 SCS1 SCS0 None (Master Port can be derived from Table ...
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IDLE CODE INSERTION The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code placed in the transmit idle-definition register (TIDR). This allows the same 8-bit code to be placed into any ...
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PER-CHANNEL LOOPBACK The DS21Q50 has per-channel loopback capability that can operate in one of two modes: remote per- channel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are looped back. In remote ...
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ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers always report the data received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated ...
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Register Name: RNAF Register Description: Receive Nonalign Frame Register Register Address: 29 Hex Bit 7 6 Name Si 1 NAME BIT Si 7 International Bit 1 6 Frame Nonalignment Signal Bit A 5 Remote Alarm Sa4 4 Additional Bit 4 ...
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Register Name: TNAF Register Description: Transmit Nonalign Frame Register Register Address: 21 Hex (Bit 6 must be programmed to 1; the DS21Q50 does not automatically set this bit.) Bit 7 6 Name Si 1 NAME BIT Si 7 International Bit ...
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USER-CONFIGURABLE OUTPUTS There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry, or access transmit ...
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Register Name: OUTBC Register Description: OUTB Control Register Register Address: 1B Hex Bit 7 6 Name NRZE — NAME BIT NRZ Enable. When this bit is set, the receiver can accept TTL-type NRZ data at the RTIP input. RRING becomes ...
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Table 15-1. OUTA and OUTB Function Select OA3 OA2 OA1 OA0 OB3 OB2 OB1 OB0 ...
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LINE INTERFACE UNIT The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register ...
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Termination The DS21Q50 is designed to be fully software-selectable for 75W and 120W termination without the need to change any external resistors. The user can configure the DS21Q50 for 75W or 120W receive termination by setting the IRTSEL (CCR5.4) ...
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Register Name: RMM Register Description: Receive Monitor Mode Register Register Address: 1F Hex Bit 7 6 Name 0 MM1 NAME BIT — 7 Reserved. Must be set = 0 for proper operation 6 Monitor Mode 2. Sets the internal linear ...
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Transmit Waveshaping and Line Driving The DS21Q50 uses a set of laser-trimmed delay lines with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (Figure ...
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Figure 16-2. External Analog Connections (Basic Configuration) E1 TRANSMIT LINE E1 RECEIVE LINE Figure 16-3. External Analog Connections (Protected Interface) Fuse TRANSMIT LINE Fuse Fuse RECEIVE LINE Fuse NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE ...
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Figure 16-4. Transmit Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 194ns 219ns -200 -150 -100 -50 0 TIME (ns 269ns G.703 Template 50 100 150 200 ...
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Jitter Attenuators The DS21Q50 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated “clock only” jitter attenuator. alternate jitter attenuator. Clock and Data Jitter Attenuators The clock and data jitter attenuators can be ...
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Figure 16-5. Jitter Tolerance 1K 100 0.1 1 Figure 16-6. Jitter Attenuation 0dB -20dB -40dB -60dB 1 Ds21Q50 Tolerance 1.5 Minimum Tolerance Level as per ITU G.823 20 10 100 1K FREQUENCY (Hz) Prohibited Area ETS 300 ...
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CMI (CODE MARK INVERSION) The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B-coded signal. Ones are alternately encoded as a logical level for the full duration of the ...
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Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMI-coded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the ...
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INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to be ...
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Table 18-2. IBO System Clock Select SCS1 SCS0 Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) Note: See Section 16 for details about the line interface circuit. FUNCTION 2.048MHz, ...
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FUNCTIONAL TIMING DIAGRAMS 19.1 Receive Timing Diagrams Figure 19-1. Receive Frame and Multiframe Timing 1 FRAME RSYNC 2 RSYNC NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). ...
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Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) SYSCLK CHANNEL 31 RSER 1 RSYNC 2 RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1). Figure ...
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Transmit Timing Diagrams Figure 19-5. Transmit Frame and Multiframe Timing FRAME TSYNC 2 TSYNC NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1). Figure ...
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Figure 19-7. Transmit Interleave Bus Operation TSYNC 1 TSER FR1 CH32 2 FR2 CH32 FR3 CH32 FR0 CH1 TSER SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 TSER NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: TSYNC ...
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Figure 19-8. Framer Synchronization Flowchart esync 1 Increm ent ync C ounter FAS R ...
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Figure 19-9. Transmit Data Flow TNAF.5-7 NOTES: 1. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent. TSER TAF 1 0 Timeslot 0 Pass-Through ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS21Q50L………………………………………………………………..0°C to +70°C Operating Temperature Range for DS21Q50LN……………………………………………………………-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………………..See IPC/JEDEC J-STD-020A Specification ...
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AC TIMING PARAMETERS AND DIAGRAMS 21.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse ...
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Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) ALE t ASD AD0–AD7 Figure 21-2. Intel Bus Write Timing (PBTS = 0) ALE t ASD AD0–AD7 t CYC PW ASH t ASED t ...
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Figure 21-3. Motorola Bus AC Timing (PBTS = ASD R/W AD0–AD7 (read) CS AD0–AD7 (write) PW ASH t ASED t RWS t t DDR ASL t AHL ASL t AHL 77 ...
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Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (V = 3.3V ± 5 0°C to +70°C for DS21Q50L PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active ...
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Figure 21-4. Intel Bus Read Timing (PBTS = 0) A0–A7 D0– 0ns (min) RD Figure 21-5. Intel Bus Write Timing (PBTS = 0) A0–A7 D0– 0ns (min) WR Address Valid 5ns (min)/20ns (max) t1 0ns (min) ...
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Figure 21-6. Motorola Bus Read Timing (PBTS = 1) A0–A7 D0– 0ns (min) DS Figure 21-7. Motorola Bus Write Timing (PBTS = 1) A0–A7 D0– 0ns (min) DS Address Valid 5ns (min)/20ns (max) t1 ...
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Serial Port AC CHARACTERISTICS—SERIAL PORT (BTS1 = 1, BTS0 = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER Setup Time CS to SCLK Setup Time SDI to SCLK Hold Time SCLK ...
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Receive AC Characteristics AC CHARACTERISTICS—RECEIVER (V = 3.3.0V ±5 0°C to +70°C for DS21Q50L PARAMETER SYSCLK Period (Note 1) SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width Delay RCLK to RSER ...
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Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled SYSCLK t D3 RSER 1 RSYNC 2 OUTA / OUTB 3 RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED ...
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Transmit AC Characteristics AC CHARACTERISTICS—TRANSMIT (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER TCLK Period TCLK Pulse Width TSYNC Setup to TCLK TSYNC Pulse Width TSER Setup to TCLK Falling TSER Hold ...
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Figure 21-11. Transmit AC Timing (IBO Disabled TCLK TSER 1 TSYNC 2 TSYNC OUTA/OUTB 3 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). NOTE ...
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Special Modes AC Characteristics AC CHARACTERISTICS—SPECIAL MODES (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER RTIP Period RTIP Pulse Width RTIP Setup to RRING Falling TSER Hold from TCLK Falling RTIP, RRING ...
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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time © 2004 Maxim Integrated Products · Printed USA ...