SI3210-BT Silicon Laboratories Inc, SI3210-BT Datasheet - Page 34

• Manufacturer Part Number: SI3210-BT
• Description: IC SLIC/CODEC PROG 38TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r
• Type: ProSLIC Programmable CMOS SLICr

Specifications of SI3210-BT

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 88mA
• Power (watts): 700mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: BORSCHT Functions, DTMF Generation and Decoding, FSK Generation, Pulse Metering Generation, Voice Loopback Test Modes
• Product: SLIC
• Supply Voltage (min): 3.13 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si3210/Si3211
34
Power Alarm Threshold, Q1 & Q2
Power Alarm Threshold, Q3 & Q4
Power Alarm Threshold, Q5 & Q6
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
Power Alarm Interrupt Pending
Power Alarm Interrupt Enable
Thermal LPF Pole, Q1 & Q2
Thermal LPF Pole, Q3 & Q4
Thermal LPF Pole, Q5 & Q6
Line Power Monitor Output
Automatic/Manual Detect
Power Monitor Pointer
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Power Alarm
Parameter
Table 25. Associated Power Monitoring and Power Fault Registers
Bits 2 to 7 correspond
Bits 2 to 7 correspond
0 to 0.9 W for Q3, Q4
0 to 5 points to Q1 to
Description/ Range
to Q1 to Q6, respec-
to Q1 to Q6, respec-
1 = enter open state
upon power alarm
0 to 7.8 W for Q1,
0 = manual mode
Q6, respectively
Q2, Q5, Q6
0 to 7.8 W
0 to 0.9 W
0 to 7.8 W
See equation above.
See equation above.
See equation above.
tively
tively
Rev. 1.45
Resolution
30.4 mW
3.62 mW
30.4 mW
3.62 mW
30.4 mW
n/a
n/a
n/a
n/a
PWRMP[2:0]
PWROM[7:0]
QnAP[n+1],
where n = 1
QnAE[n+1],
where n = 1
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
NQ12[7:0]
NQ34[7:0]
NQ56[7:0]
Register
AOPN
Bits
to 6
to 6
Indirect Register 32
Indirect Register 33
Indirect Register 34
Indirect Register 37
Indirect Register 38
Indirect Register 39
Direct Register 76
Direct Register 77
Direct Register 19
Direct Register 22
Direct Register 67
Location*