LTC4280IUFD#TR Linear Technology, LTC4280IUFD#TR Datasheet - Page 16

• Manufacturer Part Number: LTC4280IUFD#TR
• Manufacturer: Linear Technology

Specifications of LTC4280IUFD#TR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LTC4280
APPLICATIONS INFORMATION
If the system shuts down due to a fault, it may be desirable
to restart the system simply by removing and reinserting
a load card. In cases where the LTC4280 and the switch
reside on a backplane or midplane and the load resides on
a plug-in card, the EN pin detects when the plug-in card is
removed. Figure 4 shows an example where the EN pin is
used to detect insertion. Once the plug-in card is reinserted
the fault register is cleared (except for D4). After 100ms
the state of the ON pin is latched into bit A3 of the control
register. At this point the system starts up again.
If a connection sense on the plug-in card is driving the EN
pin, insertion or removal of the card may cause the pin
voltage to bounce. This results in clearing the fault register
when the card is removed. The pin may be debounced
using a fi lter capacitor, C
Figure 4. The fi lter time is given by:
FET Short Fault
A FET short fault is reported if the data converter measures
a current sense voltage greater than or equal to 1.6mV
while the GATE is turned off. This condition sets FET short
present bit, C5, and FET short fault bit D5.
16
LTC4280
t
FILTER
= C
MOTHERBOARD
OUT
Figure 4. Plug-In Card Insertion/Removal
SOURCE
EN
+
–
GND
• 123 [ms/μF]
1.235V
10μA
EN
EN
, on the ENpin as shown in
C
EN
CONNECTOR
PLUG-IN
4280 F04
CARD
LOAD
Power Bad Fault
A power bad fault is reported if the FB pin voltage drops
below its 1.235V threshold for more than 2μs when the
GATE is high. This pulls the GPIO pin low immediately
when confi gured as power-good, and sets power-bad
present bit, C3, and power bad fault bit D3. A circuit
prevents power-bad faults if the gate-to-source voltage is
low, eliminating false power-bad faults during power-up
or power-down. If the FB pin voltage subsequently rises
back above the threshold, the GPIO pin returns to a high
impedance state and bit C3 is reset.
Fault Alerts
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B has been set. This allows only selected
faults to generate alerts. At power-up the default state is to
not alert on faults. If an alert is enabled, the corresponding
fault causes the ALERT pin to pull low. After the bus master
controller broadcasts the Alert Response Address, the
LTC4280 responds with its address on the SDA line and
releases ALERT as shown in Table 6. If there is a collision
between two LTC4215s responding with their addresses
simultaneously, then the device with the lower address
wins arbitration and responds fi rst. The ALERT line is also
released if the device is addressed by the bus master.
Once the ALERT signal has been released for one fault, it
is not pulled low again until the FAULT register indicates a
different fault has occurred or the original fault is cleared
and it occurs again. Note that this means repeated or
continuing faults do not generate alerts until the associated
FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions. First,
a serial bus command writing zeros to the FAULT register
D clears the associated faults. Second, the entire FAULT
register is cleared when the switch is turned off by the ON
4280f