CY7C4811-15AIT Cypress Semiconductor Corp, CY7C4811-15AIT Datasheet - Page 8

• Manufacturer Part Number: CY7C4811-15AIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4811-15AIT

• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06005 Rev. *A
(WENB2/LDB)
RENA1, RENA2
(RENB1,RENB2)
Notes:
13. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.
14. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.
15. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make
(WENB1)
WENA2/LDA
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFB, PAFB)
QA
(QB
WENA1
RSA(RSB)
Reset Timing
0
0
the pin act as a load enable for the programmable flag offset registers.
QA
QB
8
8
)
[15]
[13]
(continued)
t
t
t
RSF
RSF
RSF
t
RS
t
t
t
RSS
RSS
RSS
t
t
t
RSR
RSR
RSR
CY7C4831/4841/4851
CY7C4801/4811/4821
OEA(OEB)=1
OEA(OEB)=0
[14]
Page 8 of 23
48X1–8
[+] Feedback