LTC3225EDDB#PBF Linear Technology, LTC3225EDDB#PBF Datasheet - Page 5

• Manufacturer Part Number: LTC3225EDDB#PBF
• Manufacturer: Linear Technology

Specifications of LTC3225EDDB#PBF

• Lead Free Status / Rohs Status: Compliant

PIN FUNCTIONS
C
or X7R ceramic capacitor should be connected from C
to C
C
CX (Pin 3): Midpoint of Two Series Supercapacitors. This
pin voltage is monitored and forced to track C
C
the top and bottom supercapacitors.
SHDN (Pin 4): Active Low Shutdown Input. A low on SHDN
puts the LTC3225/LTC3225-1 in low current shutdown
mode. Do not fl oat the SHDN pin.
PGOOD (Pin 5): Open-Drain Output Status Indicator. Upon
start-up, this open-drain pin remains low until the output
voltage, V
V
(typical) below its correct regulation level, PGOOD is
pulled low. PGOOD may be pulled up through an external
resistor to an appropriate reference level. This pin is Hi-Z
in shutdown mode.
TYPICAL PERFORMANCE CHARACTERISTICS
(T
300mA/DIV
500mV/DIV
V
+
–
OUT
OUT
TOP
A
(Pin 1): Flying Capacitor Positive Terminal. A 1μF X5R
(Pin 2): Flying Capacitor Negative Terminal.
5V/DIV
2V/DIV
= 25°C, C
V
SHDN
-V
–
COUT
/2) during charging to achieve voltage balancing of
I
.
BOT
VIN
is valid, PGOOD becomes Hi-Z. If V
Charging Profi le with Unequal
Initial Output Capacitor Voltage
(Initial V
LTC3225
V
R
C
C
C
SEL
TOP
TOP
BOT
PROG
OUT
FLY
= V
= C
INITIAL VOLTAGE = 1V
INITIAL VOLTAGE = 1.3V
= 12k
, is within 6% (typical) of its fi nal value. Once
IN
BOT
= 1μF , C
TOP
= 1.1F
= 1V, V
2 SEC/DIV
IN
= 2.2μF , C
BOT
= 1.3V)
TOP
3225 G10
= C
BOT
300mA/DIV
200mV/DIV
V
, unless otherwise specifi ed)
TOP
OUT
5V/DIV
2V/DIV
V
SHDN
-V
COUT
I
BOT
VIN
falls 7.2%
OUT
Charging Profi le with 30%
Mismatch in Output Capacitance
(C
LTC3225
V
R
C
C
C
C
SEL
TOP
BOT
TOP
BOT
PROG
TOP
(CX =
= V
= 1.43F
= 1.1F
INITIAL VOLTAGE = 0V
INITIAL VOLTAGE = 0V
= 12k
> C
IN
+
BOT
)
5 SEC/DIV
V
low at V
or 4V (LTC3225-1); a logic high sets the regulated C
to 5.3V (LTC3225) or 4.5V (LTC3225-1). Do not fl oat the
V
PROG (Pin 7): Charge Current Programming Pin. A resis-
tor connected between this pin and GND sets the charge
current. (See Applications Information section).
GND (Pin 8, Exposed Pad Pin 11): Charge Pump Ground.
These pins must be soldered directly to PCB ground. The
exposed pad must be soldered to a low impedance PCB
ground for rated thermal performance.
V
V
capacitor of more than 2.2μF .
C
the top plate of the top supercapacitor. C
current to the supercapacitors and regulates the fi nal volt-
age to 4.8V/5.3V (LTC3225) or 4V/4.5V (LTC3225-1).
SEL
SEL
IN
IN
OUT
should be bypassed to GND with a low ESR ceramic
(Pin 9): Power Supply for the LTC3225/LTC3225-1.
pin.
(Pin 10): Charge Pump Output Pin. Connect C
(Pin 6): Output Voltage Selection Input. A logic
SEL
sets the regulated C
3225 G11
LTC3225/LTC3225-1
300mA/DIV
200mV/DIV
V
TOP
5V/DIV
2V/DIV
V
SHDN
-V
COUT
I
BOT
VIN
Charging Profi le with 30%
Mismatch in Output Capacitance
(C
LTC3225
V
R
C
C
C
C
SEL
TOP
BOT
TOP
BOT
PROG
TOP
= V
= 1.1F
= 1.43F
INITIAL VOLTAGE = 0V
INITIAL VOLTAGE = 0V
= 12k
< C
IN
OUT
BOT
OUT
to 4.8V (LTC3225)
)
5 SEC/DIV
provides charge
OUT
3225fb
5
3225 G12
OUT
to