CY8C5468AXI-018 Cypress Semiconductor Corp, CY8C5468AXI-018 Datasheet - Page 4

• Manufacturer Part Number: CY8C5468AXI-018
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5468AXI-018

• Lead Free Status / Rohs Status: Compliant

Figure 1-1
family. They are:
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals. In addition to the flexibility of the UDB array, PSoC
also provides configurable digital blocks targeted at specific
functions. For the CY8C54 fa mily these blocks can include four
16-bit timer, counter, and PWM blocks; I
multi-master; FS USB; and Full CAN 2.0b.
For more details on the peripherals see the
Peripherals”
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C54 family offers two successive approximation
register (SAR) ADCs. Featuring 12-bit conversions at up to 1 M
samples per second, they also offer low nonlinearity and offset
errors and SNR better than 70 dB. They are well suited for a
variety of higher speed analog applications.
Document Number: 001-66238 Rev. *A
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
DFB
illustrates the major components of the CY8C54
section on page 31 of this data sheet. For
section on page 31 of this data sheet.
2
C slave, master, and
“Example
PRELIMINARY
The output of either ADC can optionally feed the programmable
DFB via DMA without CPU intervention. The designer can
configure the DFB to perform IIR and FIR digital filters and
several user defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
See the
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash and
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
to be set independently of V
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
PSoC
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
“Analog Subsystem”
®
2
C bus where the PSoC may not be powered when
5: CY8C54 Family Datasheet
DDIO
section on page 44 of this data
when used as outputs. When
DDIO
pins. Every GPIO
Page 4 of 105
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