MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 38

IC UART SPI/I2C 128 FIFO 24SSOP

MAX3107EAG+

Manufacturer Part Number
MAX3107EAG+
Description
IC UART SPI/I2C 128 FIFO 24SSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX3107EAG+

Features
Internal Oscillators
Number Of Channels
4, QUART
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.35 V ~ 3.6 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
Mounting Type
Surface Mount
Package / Case
24-SSOP
Data Rate
24 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.71 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 3. SwFlow[3:0] Truth Table
SPI/I
and Internal Oscillator
X = Don’t care
XON1 Register
The XON1 and XON2 register contents define the XON characters used for auto XON/XOFF flow control and/or the
special characters used for special character detection. See details in the FlowCtrl register description.
Bits 7–0: Bit[7:0]
These bits define the XON1 character if single-character XON auto software flow control is enabled in FlowCntrl[7:4].
If double-character flow control is selected in FlowCntrl[7:4], these bits constitute the LSB of the XON character. If
special character detection is enabled in MODE2[4] and auto flow control is not enabled, these bits define a special
character. If special character detection and auto software flow control are enabled, XON1 defines the XON flow con-
trol character.
38
ADDRESS:
MODE:
SwFlow3
RESET
NAME
_____________________________________________________________________________________
BIT
0
0
1
0
1
X
X
X
X
RECEIVER FLOW
CONTROL
2
C UART with 128-Word FIFOs
SwFlow2
Bit7
7
0
0
0
0
1
1
X
X
X
X
0x14
R/W
Bit6
6
0
CHARACTER DETECTION
SwFlow1
TRANSMITTER FLOW
CONTROL/SPECIAL
0
X
X
X
X
0
1
0
1
Bit5
5
0
SwFlow0
X
X
X
X
0
0
0
1
1
Bit4
4
0
No flow control/no character detection.
No receiver flow control.
Transmitter generates XON1, XOFF1.
Transmitter generates XON2, XOFF2.
Transmitter generates XON1, XON2, XOFF1, and XOFF2.
No transmitter flow control.
Receiver compares XON1 and XOFF1 and controls the
transmitter accordingly. XON1 and XOFF1 special character
detection.
Receiver compares XON2 and XOFF2 and controls the
transmitter accordingly. XON2 and XOFF2 special character
detection.
Receiver compares XON1, XON2, XOFF1, and XOFF2 and
controls the transmitter accordingly. XON1, XON2, XOFF1,
and XOFF2 special character detection.
Bit3
3
0
DESCRIPTION
Bit2
2
0
Bit1
1
0
Bit0
0
0

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